Adding bidirectional I2C digital isolation to your embedded design - Embedded.com

Adding bidirectional I2C digital isolation to your embedded design

This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.

Historically, designers have used opto- couplers for I2C isolation.These circuits are somewhat complex, sensitive to bus capacitance andlimited in speed. They are also not compatible with high speed digitalisolators having standard CMOS input levels.

This design idea shows how to convert a standard high speed digitalisolator to a bidirectional I2C isolator. In addition to beingcompatible with digital isolators, the circuit is simpler than previouspublished solutions, completely insensitive to bus capacitance and itcan easily support the standard 400KHz maximum I2C bus rate.

Standard I2C SDA and SCL signals are driven by open drain drivers.In all cases, SDA can be driven by any device on the bus so that theSDA bus wire communicates information from the I2C master to the slavesand from the slaves to the master. That is, the data transfer isbi-directional. In some cases, the SCL only has a driver for the I2Cmaster.

However, in many cases such as multiple I2C masters or if the slaveneeds to stretch SCL by holding it low while it retrieves data then theSCL line must also be bi-directional.

For the wires that need to be bidirectional, if digital isolatorsare inserted there are several problems; the isolators must be opendrain, and there is a latch up condition that can occur. If, forexample, the side A driver pulls low then isolator A pulls low on sideB.

This causes isolator B to pull low on side A and the circuit latcheswith both isolators pulling low. The open drain problem is easilysolved by putting a Schottky diode in series with the isolator output.However, the latch up problem is much more difficult to solve.

Previous attempts to solve this problem have used diodes inherent tothe opto-coupler input and additional circuitry to avoid the latch-upcondition. Some of these approaches are sensitive to bus capacitance.

They tend to be slow due to the slow response of the opto-couplers.Finally, when higher speed digital isolators with standard CMOS inputlevels are used, the circuit tricks using the diode input of theopto-couplers no longer apply.

Circuit using digital isolators
The full circuit using a Silicon Laboratories, Inc. Si8442 high speedisolator is show in Figure 1 below .The circuit assumes 1K pull upresistors on the SCL and SDA lines. It can be easily adjusted for otherbus pull up resistors. This circuit has been tested with SiliconLaboratories, Inc. C8051Fxxx series MCUs at a bus speed ofapproximately 300KHz including bus transactions which require SCL clockstretching.
 

Figure1: Diodes D1A, B and D2A, b convert the push-pull output of the Si8442to open drain.

(Clickhere to to see a enlarged view )

The latchup problem described above is solved by using a comparatorto sense whether the non-isolated side (side A) is causing the low onthe isolated side (side B). Transistors Q1 and Q2 act as thecomparators. If the low on side B is caused by low on side A, Q1 or Q2will not turn on due the drop across diodes D2A,B and R1 or R2 and thelow is not propagated back to side A breaking the latch condition.

If the low on side B is caused by the open drain driver on side B,Q1 and Q2 do turn on and the low is propagated. Note that thecomparator circuit only needs to be used on one side, and could be usedon either side A or side B. The voltage levels on Side A are completelycompatible with I2C requirements and there is no special considerationfor the side without the comparator circuit.

For side B, with the comparator circuit, the output of the isolatorshould not turn on the comparator but the open drain driver must turnon the comparator. The threshold of the comparators is set by thevoltage dividers R3,R4 and R6,R7. Diodes D3A,B provide temperaturecompensation to match diodes D2A,B.

With the component values shown, the comparator threshold isapproximately 0.28V. The schottky clamp pulls down to approximately0.5V and the open drain driver pulls to typically 0.1V so thecomparator threshold is well centred between these values.

If the bus pull up resistors are not 1K , the Vdd voltage is not3.3V or if the driver on the side with the comparator cannot pull below0.2V, the circuit will need to be adjusted. The pull down from theisolator (as determined by diode D2 and R1 or R2) must be adjusted tobe compatible with the logic low of the devices connected to the bus onside B.

The comparator threshold is set by D3 (to track D2) and the voltagedivider R3/R4 or R6/R7. The comparator threshold is adjusted to centrebetween the pull down of the isolator circuit and the pull down of theother I2C circuits on the I2C bus on side B.

Circuit performance
The propagation delay from side A (non-isolated side) to side B(isolated side) introduced by the isolator circuit is negligible(<50nsec) for both rising and falling edges. This is because in thisdirection, the comparator is not in the path and introduces no delay.

For the falling edge, the delay is approximately 50nsec as thetransistor switches on. For the rising edge there is a delay ofapproximately 250nsec as the transistor switches off. Also note that inthis case, the final rise of the input waveform is delayed so that theskew as the waveforms cross a typical 1V CMOS logic threshold is quitesmall.

The added delay introduced by this circuit is compatible with I2C orSMBus operation at speeds up to 400KHz. Therefore, using a digitalisolator for I2C isolation provides many benefits to the designer overthe traditional implementations.

John Gammel is with SiliconLaboratories.

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