Addressing embedded hardware design challenges through informed design decisions - Embedded.com

Addressing embedded hardware design challenges through informed design decisions

What are the five primary and interconnected design decisions that must be addressed during the hardware design cycle?

Embedded hardware designers face a wide range of design challenges and options requiring many trade-offs and decisions. The design team must adjust their approach to accommodate program logistics, design requirements, and technology limitations. Program logistic challenges include aggressive schedules, product price goals, smaller staffs, and extended product life-cycle expectations. Design challenges include interface bandwidth, performance goals, size limitations, power constraints, and implementing sufficient design margin.

Added to these challenges is the pressure to produce single-pass production-ready designs that include the flexibility required to support future design updates and enhancements without significant hardware changes. These decisions are further complicated by the fact that many design phases and decisions are interrelated, affecting multiple areas of a design. At the highest level, there are five primary design decision areas that must be addressed during the hardware design cycle. These areas include design management, system design, design leverage, design flexibility, and board level design.

Design management is the art of managing design requirements, budget, schedule, staffing, system, and unit costs. System design involves selecting the right design architecture to implement the required functionality. This requires selecting the right technologies, device families, design tools, and allocation of functionality between system blocks. The system level is where modular design blocks and design reuse strategies should be selected. Design leverage takes advantage of reference designs, interface standards, existing protocols and Intellectual Property (IP) offerings. Design flexibility involves incorporating design elements that support low overhead design reconfiguration and end-product updates. Flexible technologies include processors and programmable logic with functionality implemented by firmware and HDLs. Board-level design is the implementation of the lowest level of design functionality. Tasks include part selection, mixed signal design, power design, noise mitigation, thermal issues, and real-estate management.

The decisions made in each of these design areas can either carry a design team through a successful product development or divert time and effort leading to extended schedules and budgets and limited design functionality. The Boston Embedded Systems Conference Hardware Design track has been developed to address concerns within each of these decision areas and provide guidance for overcoming some of the most common hardware design challenges.

Design Decision Group
Design Management

  • Build vs. Buy: Custom, COTS, & Caveats

System Design

  • Twenty-five Lessons Learned in Hardware/Firmware Interface Design
  • Prototyping and System Development with FPGAs

Design Leverage

  • Implementing an 802.11 b/g Interface into an Embedded Design

Design Flexibility

  • Implementing Downloadable Firmware with Flash Memory
  • Introduction to VHDL

Board-Level Design

  • Noise and Shielding
  • Managing Power, Ground and Noise in Microcontroller/Analog Applications

These classes can help prepare your design team members to make informed trade-offs and decisions that lead to the best design solutions with a minimum of effort and schedule. We look forward to seeing you at this year's Boston Embedded Systems Conference.

RC Cofer is a field application engineer for Avnet with 17 years of embedded design experience including real-time DSP algorithm development, board design, debug and integration, transition to volume production, systems engineering, and embedded design project management. His technical focus is rapid system design and prototyping. Utilizing FPGAs in designs allows maximum flexibility while also reducing risk and schedule. He holds a BSEE from Florida Tech and a MSEE in communications and DSP from the University of Florida.

Ben Harding has over 15 years of embedded hardware and software design experience with FPGAs, DSPs, network processors, parallel processing, various OS/RTOS solutions, low level code implementation and algorithm development. He has a BSEE from UAH with extensive post graduate studies in DSP, digital design, control systems, digital communications, parallel processing, and robotics. He is a co-author of Rapid System Prototyping with FPGAs, Elsevier 2005. Ben was an active member of the US Army before beginning his engineering career at the US Army Aviation and Missile Research Center. He is currently a senior FAE at Avnet.

Register here for ESC Boston track classes. The conference will be held September 18 to 21 at the Hynes Convention Center, Boston, MA. If you can't attend ESC Boston and are interested in these tracks, you can download track presentations for a fee from Embedded on Demand after the show.

Here's an overview of all the tracks at ESC Boston.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.