Addressing EMI test challenges in nextgen high density interconnect PCB design -

Addressing EMI test challenges in nextgen high density interconnect PCB design


As engineers, you need to incorporate advanced technologies into products to make them superior in functionality or optimized for product cost. The challenge lies in how to efficiently implement these technologies into the products while considering factors such as time-to-market, design features, testing and EMI conformity.

Depending on how much upfront work has been done, implementing several iterations in the design is possible. Often, if problems are caught later in the design cycle, it becomes more difficult to redesign. Many companies know that getting a tightly integrated design tool is important, but often it is greatly compromised by cost.

This article discusses how to address the challenges in PCB design and what factors should be considered when evaluating a PCB design tool.

Keep these factors in mind
There are many factors to consider during PCB evaluation. The tools to be used must be selected based on the complexity of the design. As systems grow in complexity, the need to control physical routing and electrical elements also grows, paving the way for constraint entry to become a critical path in the design process.

However, too many design constraints can restrict design flexibility. Engineers must understand their design and design rules so they know when to be flexible with them.

Figure 1: A typical integrated system design starts with design definition or schematic entry.

A typical integrated system design starts with design definition or schematic entry. The design definition is tightly integrated with Constraint Editing, where designers can define both physical and electrical constraints. The electrical constraint will drive the simulator for net verification for both pre-layout and post-layout analyses.

Looking closely at the design definition, you will note that it is also linked to FPGA/PCB Integration, which aims to provide bidirectional integration, data management and the ability to perform concurrent design between FPGA and PCB.

In the layout stage, the same constraint rules entered during the design definition are used for physical implementation. This reduces the possibility of error-prone paper-to-layout. Pinswap, gate-swap and even the IO. Bank-swap must be updated back to the design definition so the designs are synchronized.

During evaluation, the designer should consider which factor ranks the most important. Here's a list of trends that designers must consider when evaluating the capability of their existing tools or when sourcing around for new ones.

1. High density interconnect (HDI). Semiconductor complexity and increase in the total number of gates have required more pins for ICs as well as finer pin pitch. At present, it is common to have over 2,000 pins on a 1mm pitch BGA and 296 pins on a 0.65mm pitch device.

The demand for faster rise-times coupled with the need for SI requires an increasing number of power and ground pins. Consequently, this drives the need for layers in multilayers and the need for HDI with microvias.

HDI is the interconnect technology that is being developed to meet these needs. Microvias are the principal feature of HDI, along with thinner dielectrics, and smaller traces and spaces.

2. RF design. The RF circuits should be designed directly into the system schematic and the system board layout rather than in a separate environment for later translation.

All the simulation, tuning and optimization capabilities of the RF simulation environment are still needed, but the simulation environment can be fed with much more primitive data than the actual design. Hence, differences between data models and the issues of design translation are eliminated.

First, designers can crossprobe directly between system design and RF simulation. Second, if designers have a large or complicated RF design, they can distribute the circuit simulation to multiple computing platforms to run them in parallel and thus, shorten simulation time. Alternatively, they can send each circuit in a multi-module design to a separate simulator.

3. Advanced packaging. The increasing functional complexity of modern products has required an equivalent increase in passive devices, primarily in the form of decoupling capacitors and terminating resistors for low-power, high-frequency applications.

While SMD packages for passives have shrunk considerably over the years, the answer is still the same when trying to achieve maximum density – bury them. Printed components made the transition from MCMs and hybrids to today's system-in-package and PCBs as embedded passives.

Along the way, they have been adapted to current fabrication techniques. For example, the inclusion of a resistive material layer within a core laminate structure and the creation of series termination resistors directly underneath microBGA packages, have improved circuit performance.

Embedded passives can now be designed with tight tolerances to avoid laser trimming in manufacturing. Wireless components are also seeing increased integration within the substrate.

4. Rigid-flex PCB. To design a rigid-flex PCB, all factors that impact the fabrication process must be considered. Engineers cannot simply design a rigid-flex PCB as if it were just another rigid PCB.

They must manage the bend areas of the design to ensure that design elements will not lead to stress fractures or delaminating of the conductors from the forces of the bend. There are also mechanical factors to consider such as minimum bend radii, dielectric thickness and type, foil weight, copper plating, overall circuit thickness, number of layers and number of flexures.

Understanding rigid-flex design and determining whether the product allows you to create a rigid-flex design is important.

5. Planning for signal integrity. New technologies have evolved in recent years with regards to parallel-bus architecture and differential-pair architecture for Serdes or serial interconnects.

Figure 2 below shows the type of typical design issues for a parallel bus and the Serdes design. The limitation of a parallel bus lies in system timing variations such as skew and propagation. Designing to the timing constraint is already difficult because of the skew across the bus width. Increasing the clock speed would only worsen the problem.

Figure 2: The limitation of a parallel bus lies in system timing variations such as skew and propagation.

Meanwhile, differential pair architecture uses serial communications with a switched point-to-point connection at the hardware level. In general, it moves data across unidirectional serial “lanes,” which are stackable into 1-, 2 -, 4 -, 8 -, 16 – and 32-wide configurations.

Each lane carries 1byte of a word so the bus can handle 8bit to 256bit data widths, and data integrity is preserved through the use of an error detection technique. However, due to high-speed rate, other design issues arise. Clock recovery at high frequencies puts a large burden on the system's ability to lock the clock to the incoming data stream quickly, and it reduces overall cycle-to-cycle jitter to improve the jitter tolerance of the circuit.

Noise on the power supply creates an additional problem for designers. This type of noise increases the likelihood of having significant amount of jitter, making the eye opening even more difficult to obtain. Other challenges include reducing common- mode noise and tackling the problems of lossy effects from IC packaging, boards, cables and connectors.

6. Availability of design kits. Having design kits of USB, DDR/DDR2, PCI-X, PCIe and Rocket IO will be helpful to designers making a transition into new technologies. Design kits give an overview of technology and specification details. It also gives information about the design issues that the engineer will face, followed by simulation and how to create routing constraints.

This gives a headstart to designers, giving them an edge for adopting new technologies. Getting a PCB tool that can handle the layout is easy; getting a tool that not only satisfies the layout, but also addresses the designer's nearend needs is also important.

Sylvia Teo is Senior Applications Engineer at Mentor Graphics Asia Pte Ltd

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