Agilent EEsof EDA’s Controlled Impedance Line Designer from Agilent Technologies Inc. optimizes stack up and line geometry for multigigabit-per-second chip-to-chip links, using the most relevant metric. The product, available as an add-on to Advanced Design System 2014, uses a novel approach to design controlled impedance transmission lines. Previous tools for this task allowed only for line characteristics, such as frequency response, as the optimization goal. In modern chip-to-chip links, this metric has become less relevant because it doesn’t take holistic effects of the end-to-end link into account. Most important, the effect of the equalizer in the receiver is ignored. The metric that matters today is the post-equalization eye opening.
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The integration of Agilent’s Controlled Impedance Line Designer and the existing Channel Simulator in ADS rectifies this situation by letting engineers see a set of eye openings that result from sweeping through the pre-layout design parameters (e.g., line width). To ensure accurate calculation of the transmission line characteristics, the software automatically employs a fast, cross-sectional (2D) electromagnetic field solver. The dielectric layers are modeled using the frequency-dependent Svensson/Djordjevic permittivity, which ensures both accuracy and delay causality. The metal layer model accounts for conductivity, skin effect, and top and bottom surface roughness.
The Controlled Impedance Line Designer also includes a provision to determine the effect of manufacturing variation on input parameters, such as thickness on the output parameters (e.g., impedance).
Agilent will demonstrate the Controlled Impedance Line Designer software for the first time in Santa Clara at DesignCon 2014, Jan. 28-31, Booth 201 .