Paris-based EDA startup Intento Design has introduced an artificial-intelligence (AI) based tool that calibrates the extracted substrate model for any foundry design kit, combining AI and machine learning with solid-state physics. The company said this addresses an industry need fast and accurate early failure prediction, critical in automotive/aerospace, as well as power management, medical, and defense applications.
The new tool, called ID-Calibre, is an extension to its ID-Substrate reliability tool for early detection and prevention of all substrate parasitics. While ID-Substrate models a substrate of a complete chip as an active 3D physical model in just a few seconds, ID-Calibre calibrates the extracted substrate model. This then accelerates accurate prediction of all potential substrate failure areas detected by ID-Substrate, while also eliminating test structure fabrication and foundry measurement expenses.
Ramy Iskander, CEO and founder of Intento Design, clarifies how ID-Calibre opens new market opportunities: “ID-Calibre eliminates the need for empirical calibration or test structure fabrication, effectively bringing better market competitiveness and increased ROI to IDMs, fabless, and design houses. Think of ID-Substrate/ID-Calibre as a behavioural TCAD simulation of a complete AMS chip 1000x faster than traditional TCAD finite element methods.”
Intento Design is focused on design tools and software for analog design automation. Among its products, ID-Substrate detects areas in a substrate where reliability is at risk. It extracts a netlist of parasitics to help a designer back annotate to the original netlist or re-simulate the schematic, taking into account the substrate parasitics, and visualize the areas of potential hot-spots for post-fabrication latch-up risks.
Unlike finite element modelling techniques, where simulations can last days, Intento Design says ID-Substrate simulations give accurate results in seconds. This is based on circuit-based modelling, which combined with adaptive meshing algorithms optimizes the number of elements, producing results quickly without convergence issues or accuracy losses. ID-Substrate operates within the Cadence analog design environment.
The images below illustrate how the combined ID-Substrate/ID-Calibre solution predicts substrate failures and guides layout adjustment before tape-out and fabrication. A power-on-reset (POR) signal is systematically generated when the chip is powered on. ID-Substrate analysis detected the problem area and layout adjustment was performed to protect the POR block from minority carriers induced by the output driver resistor switch. The extraction time was 1.606 seconds for a total of 2016 diodes, 8283 resistors, and 3309 homojunctions.