SAN JOSE, Calif. — A startup in India announced ambitious plans to design and license RISC-V-based processor cores as well as deep-learning accelerators and SoC design tools. InCore Semiconductors will make its first cores available before the end of the year.
The effort marks a small but significant addition to the RISC-V ecosystem. It shows that the initiative is gaining global interest for its open-source instruction set architecture as an alternative to offerings from Arm and other traditional suppliers.
InCore spun out of the Shakti processor research team at IIT-Madras, leveraging research in machine learning at its Robert Bosch AI Centre. So far, it is funding itself with revenues from providing commercial support for Shakti cores, according to G. S. Madhusudan, chief executive of InCore and a principal scientist at IIT-Madras.
The startup is developing two families of in-order cores that target edge systems ranging from ultra-low-power IoT to desktops.
At the low end, its E-class cores use three-stage pipelines and come in 32- and 64-bit versions supporting a subset of the RISC-V ISA. They will run at less than 200 MHz and come with ports of FreeRTOS, targeting Arm’s M-class cores.
The high-end, 64-bit C-class cores use a five-stage pipeline and support the full RISC-V ISA and virtualization. They target speeds up to 800 MHz but can be customized to run up to 2 GHz and issue two instructions per cycle.
The C-class cores will support a level-four secure version of Linux and target Arm’s A35/A55 cores. The startup also plans a set of extensions for the C-class cores that enable fault-tolerant functions for automotive and other markets.
Versions of both E and C cores will be available before the end of the year. Superscalar and dual-issue capabilities will be available before April.