AImotive shows 98% edge vision efficiency on Nextchip Apache5 - Embedded.com

AImotive shows 98% edge vision efficiency on Nextchip Apache5

Automotive driving software and intellectual property company AImotive said it has successfully demonstrated automotive neural network vision applications executing at up to 98% efficiency on its aiWare3P neural network processor used on Nextchip’s latest Apache5 imaging edge processor.

The company claims this is as much as 2x-3x better than other NPUs (neural network processor units) targeting automotive inference. Also featuring an advanced ISP supporting imaging sensors up to 5.7Mpixel resolution, quad-core Arm A53 CPU and small package size of only 9mm by 9mm, Nextchip’s Apache5 is aimed at demanding automotive edge vision applications to full AEC-Q100 Grade 2.

AImotive and Nextchip said the rapid bring-up of all key functions on Apache5, complemented by aiWare Studio’s unique offline NN (neural network) optimization tools, meant they were able to demonstrate to lead customers the Apache5 IEP executing demanding automotive AI applications using the aiWare NPU within weeks of receiving first samples. These confirm that Apache5’s aiWare3P 1.6 TOPS NPU can deliver up to 98% sustained real-time efficiency for a wide range of NN workloads. Only minimal optimization effort was required, which was completed prior to receipt of the first devices.

AImotive Apache5 block diagram
The Apache5 imaging edge processor block diagram.

Nextchip’s CMO, Young Jun Yoo, said, “We are excited that thanks to the close collaboration between Nextchip and AImotive, we have been able to demonstrate Apache5 executing compelling automotive AI applications with exceptional efficiency within weeks of receiving first samples.

At AImotive, the senior vice-president for hardware engineering, Márton Fehér, said, “With Apache5 we have demonstrated that we can deliver 2x to 3x higher CNN performance for the same claimed TOPS of other NPUs. Furthermore, our aiWare Studio SDK enabled our aiDrive team to bring up multiple well-optimized NNs within days of receiving Apache5 silicon.”

The Apache5 IEP (imaging edge processor) for advanced ADAS addresses a range of automotive applications, including, driver monitoring systems (DMS), smart rear view (SRV), autonomous emergency braking (AEB), lane departure warning system (LWDS), and lane keeping assist system (LKAS).

The aiWare NPU was developed by engineers working side-by-side with automated driving teams to create a solution targeting high performance L2-L4 automotive grade real-time AI inference for AD/ADAS. As a highly autonomous engine placing minimum demands on the host CPU, aiWare can be either integrated within a system on chip (SoC) or as the primary computation unit of a standalone NPU chip. Core performance, on-chip memory, floorplan, external memory bandwidth and other parameters are configurable to optimize performance for a wide range of customer requirements. The latest aiWare3P IP core is a 3rd generation design.

The aiWare Studio is a tool for taking NNs from prototype to production by helping production engineers optimize the underlying AI to maximize the system performance, not just the low-level code that executes it, said AImotive.


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