Aldec cuts ASIC design prototype bring-up time with HES-DVM’s automatic partitioning tool

Aldec has introduced automatic FPGA partitioning to its HES-DVM; the company’s fully automated and scalable hybrid verification environment for SoC and ASIC designs. Traditionally, and subject to design complexity and constraints, the manual partitioning of multiple FPGAs used for prototyping can take days, or even weeks, whereas the automation in HES-DVM can perform the task in minutes; ideal for exploratory, What-If scenarios.

The latest release of HES-DVM, 2019.09, also features Aldec’s proprietary HDL compiler. Called SyntHESer, and announced earlier this year, in a recent in-house bench test, the compiler performed 10x faster than a leading standalone synthesis tool, when handling identical blocks of HDL for a circa 45-million-gate Deep Learning Accelerator (DLA) design. For the 2019.09 release of HES-DVM, Aldec engineers designed and implemented fast and efficient algorithms capable of finding balanced partitions and minimizing required interconnections.

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