At CES 2013 Allegro DVT took the wraps off what it claims is the first hardware IP implementation of the High Efficiency Video Coding (HEVC) spec, alias H.265, the next generation video coding standard.
Currently being developed by the JCT-VC team, a joint effort between the Moving Pictures Experts Group and the ITU’s Video Coding Experts Group, the finalized HEVC standard will bring up to 50% bitrate savings compared to equivalent H.264/AVC encodings.
Alegro is demonstrating its HEVC Video Hardware Decoding IP, which its engineers say can be implemented both on FPGAs and SoCs, and supports any resolution up to 4K. They say the hardware IP has been optimized in terms of silicon area, power consumption and memory bandwidth.
HEVC replaces macroblocks, which were used with previous standards, with a new coding scheme that uses larger block structures of up to 64×64 pixels and can better sub-partition the picture into variable sized structures, important in the variety of platforms which will be making use of video: large screen and Internet TVs, laptops and PCs, smart phones, tablet computers and dedicated media players.
HEVC initially divides the picture into coding tree units (CTUs) which are then divided for each luma/chroma component into coding tree blocks (CTBs). A CTB can be 64×64, 32×32, or 16×16 with a larger block size usually increasing the coding efficiency.
CTBs are then divided into coding units (CUs). CUs are then divided into prediction units (PUs) of either intra-picture or inter-picture prediction type which can vary in size from 64×64 to 4×4.
The prediction residual is then coded using transform units (TUs), containing coefficients for spatial block transform and quantization and which can be 32×32, 16×16, 8×8, or 4×4.
Allegro’s current implementation fully complies with the latest available HEVC reference software (HM 9.1), and will be continuously updated until the HEVC standard is finalized, allowing its customers to tape-out soon after the final release of the new standard.