Alliance eases hardware/software conflicts - Embedded.com

Alliance eases hardware/software conflicts

ABINGDON, England — An alliance is set to extend Celoxica C-based synthesis technology to the IPFlex Digital Application Processor/Distributed Network Architecture (DAPDNA) dynamically reconfigurable processor technology.

Phil Bishop, Celoxica CEO, said, “Both companies are dedicated to the rapid implementation of software algorithms into high-performance dynamically reconfigurable hardware. Celoxica brings the hardware compilation technology and the system tools focus that will extend and maintain the system design flow for IPFlex users.”

The alliance has already resulted in a C-language to reconfigurable hardware compiler based on Celoxica technology. The compiler provides a high-productivity design environment for developing applications on DAPDNA hardware.

The IPFlex DAPDNA-FW II version 2.3 integrated development environment, including the new compiler, will be demonstrated at the Design Automation Conference in June.

IPFlex was founded to solve the often-conflicting concepts of software flexibility and hardware performance. The company's DAPDNA technology enables systems described in software languages, such as C, to be implemented in silicon devices with performance equivalent to custom-designed chips, with a combination of its FW II design tool and the DAPDNA-2 dynamically reconfigurable processor.

Tomoyoshi Sato, CTO of Tokyo based IPFlex. “Developers can use C language descriptions to target the DAPDNA-2 dynamically reconfigurable processor and achieve immediate results in silicon with performance comparable to custom devices.”

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