In its newest just introduced Aria 10 FPGAs, Altera Corp. has integrated hardened IEEE 754-compliant, floating-point operators and blocks that will not only lower costs of DSP in high end medical and radar applications but make them more practical in such cost sensitive applications such as wireless base station designs.
In addition to the already shipping 20 nm Arria 10 FPGAs and SoCs, the blocks are also incorporated into the 14 nm Stratix 10 FPGAs and SoCs.
According to Alex Grbic, director of software, IP and DSP marketing at Altera, the integrated hardened floating-point DSP blocks, combined with an advanced high-level tool flow, enable developers to address an expanding range of computationally intensive applications, such as high-performance computing (HPC), radar, scientific and medical imaging.
He said the hardened single-precision floating point DSP blocks included in Arria 10 and Stratix 10 devices are based on variable precision DSP architecture which feature a 64 bit accumulator each block of which comes with a 64 bit cascade bus. The cascade bus allows the implementation of even higher precision signal processing through cascading multiple blocks using a dedicated bus.
The variable-precision DSP architecture maintains backward compatibility. It can efficiently support existing 18 bit DSP applications, such as high-definition video processing, digital up- or down- conversion and multirate filtering.
“Unlike traditional approaches that implement floating point by using fixed point multipliers and FPGA logic, ” he said, “hardened floating point DSP blocks eliminate nearly all the logic usage required for existing FPGA floating-point computations. What this means, says Grbic, is the ability to deliver up to 1.5 TeraFLOPs (floating point operations per second) DSP performance in Arria 10 devices and up to 10 TeraFLOPs DSP performance in Stratix 10 devices.
Where previously DSP designers in cost sensitive but critical applications such as wireless base stations were unable to use floating point because of cost and implementation complexity, they can now choose either fixed or floating-point modes and be sure the floating point blocks are backwards compatible with existing designs.
” FPGAs feature a fine-grained, highly pipelined architecture that make them ideally suited for use as high-performance compute accelerators,” said Grbic, the inclusion of which allows developers use them for complex HPC problems in big data analytics, seismic modeling for oil and gas industries and financial simulations.
He claims the integration of hardened floating-point DSP blocks can reduce development time on FPGA-based designs by upwards of 12 months because developers can translate their DSP designs directly into floating-point hardware, rather than converting their designs to fixed point.
As a result, timing closure and verification times are dramatically slashed. The company has also developed multiple tool flows that allow hardware designers, model-based designers and software programmers to easily target the high-performance floating-point DSP blocks in its devices. Key to this integration, he said, are::
*the DSP Builder Advanced Blockset with a model-based design flow that allows designers to go from system definition and simulation to system implementation in a matter of minutes using the industry-standard MathWorks Simulink tools.
* the use of OpenCL which will make it easier for software developers to program
*A publicly available C-based, high-level design flow that targets FPGAs.