Altera ships largest APEXII -

Altera ships largest APEXII

Altera has released the APEXII EP2A70, its largest programmable logic device (PLD). It provides data transfer rates of up to 1Gbit/s True-LVDS on 36 channels and the ability to support data bandwidths up to 366 Gbits/s.

The EP2A70 device is also the first PLD to use 0.13 all-layer copper interconnect providing both increased core performance and a sustainable long-term, low-cost high-density model.

APEXII is Altera's high-performance, high-density PLD family for system-on-a-programmable-chip (SOPC) applications.

The PLDs support I/O interfaces such as RapidIO, Utopia IV, POS-PHY Level 4, HyperTransport and Flexbus. Features include dedicated serialisation/deserialisation (SERDES) and clock data-synchronisation (CDS) circuitry that make 1Gbit/s differential signaling possible for high-speed I/O capabilities, needed in high performance communications applications.

The devices architecture also provides up to 1.1Mbits of internal memory creating a solution for memory-intensive applications, such as packet processing.

The APEX II device family, first introduced in April 2001, expanded Altera's PLD logic capacity to over 89,000 logic elements (LEs) and 1.5Mbits of on-chip RAM.

Designed to optimise system performance across a range of high-performance communication applications, it allows APEX II devices to be used as a 'customisation engine' to bridge different communications protocols.

The devices can integrate a range of communication protocols such as POS-PHY L4, HyperTransport, Utopia L4, Flexbus L4, CSIX, and RapidIO. As a result, family members can interface directly to ASSPs, packet processors, host processors and other standard functional blocks found in communication systems.

This ability to address so many of the emerging high-speed I/O protocols allows all of the benefits of SOPC-based design to be realised directly in high-speed datapaths.

The enhanced I/O capability enables APEX II devices to support both 1Gbits/s True-LVDS channels (low voltage differential signaling) and 624Mbit/s Flexible-LVDS channels. These channels support the popular LVDS, LVPECL (low-voltage pseudo-emitter-coupled logic), PCML (pseudo current mode logic) and HyperTransport interfaces.

The PLDs provide up to 124 input and 124 output channels of high-performance differential I/O support.

High-performance single-ended I/O standards such as HSTL Class I, II at 250MHz are also supported and, when combined with the differential I/O capability of the devices, totals almost 380Gps of total device bandwidth.

The APEX II architecture contains a proprietary technology, clock-data synchronisation (CDS), to allow a variety of new, board-level differential clocking topologies.

Manufactured on TSMC's state-of-the art 0.15-micron all-layer copper process, the PLDs deliver increased logic capacity and performance through a combination of architecture and process technology. The APEX II devices have up to 1.5 Mbit of true dual-port RAM on chip, and the I/O cells are designed to support the fastest leading-edge external memory interfaces such as ZBT SRAM, QDR SRAM, and DDR.

Over 135 IP cores are available from Altera and its AMPP partners in the areas of signal processing, communications, and embedded systems for APEX II devices. High-speed communications interface IP solutions are available such as POS-PHY L4, HyperTransport, and RapidIO to take advantage of the advanced I/O featured in APEX II devices.

Altera's Nios core, an embedded processor soft core, has also been ported to the APEX II architecture, allowing it to take advantage of the unique capabilities of the APEX II family.

Quartos 2.0 boost SOPC designs

The latest release of Altera's QuartusII design software provides a 15% improvement in design performance and a 50% reduction in compile times. Version 2.0 also minimises time-consuming design verification tasks to help engineers accelerate their system-on-a-programmable-chip (SOPC) designs. These capabilities apply to all Altera high-density programmable logic devices (PLDs), including the APEXII device family.

Performance improvements of up to 25% are provided through an enhanced hierarchical LogicLock block-based design methodology. This design flow provides complete control of block placement to the designer, if required, allowing user-assisted floor planning. It also maintains system performance during construction of large SOPC designs by allowing designers to optimise and lock in the performance of each design block individually.

A fast fit compile option provides on average a 50% compile time benefit over the default compile settings in version 2.0. The fast fit feature accelerates compile times by conserving the effort typically applied to achieve the best performance. The result is fewer iterations of the fitting algorithm during placement and a much faster compile time with a minimal impact on design performance.

Engineers on UNIX-based networks will gain an additional compile time bonus. Sophisticated compression techniques applied to the QuartusII software result in dramatic reductions in the data transferred across networks.

The same compression techniques resulted in a more than 60% reduction in the size of the installed software on a UNIX platform. This reduction lowers the overhead associated with managing the QuartusII design software across a corporate network with multiple users.

SignalProbe technology allows users to incrementally route an internal node to an unused pin for analysis while fully preserving the design's original routing, timing, and design files.

Published in Embedded Systems (Europe) February 2002

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.