High-Level Synthesis (HLS) has broken into the main stream with FPGA vendors and EDA companies offering tools which convert C, C++, System C and Matlab into FPGA bit streams. For hybrid SoCs, the same high-level language lets us design both the processor and the programmable logic and move design elements between the processor and FPGA fabric. Part 1 of this series looked at one such HLS tool: SDSoC from Xilinx. In that article, we asked readers to select the algorithm for implementation with SDSoC.
In answer to the question if the first SDSoC example should focus upon a filter or transfer function implementation, it seems that most readers would prefer to see the FIR filter implementation. So are going to look at how we can create that system and then how we can boost its performance in the programmable logic side of the Zynq with the click of a few buttons.
Before we can implement the algorithm we must first know what we are going to implement and design it appropriately. FIR Filters are a commonly used type of digital filter, one of the great advantages about using digital filters is that we can implement most types of responses – try doing that in analog. Of course in the digital domain we do not also suffer from the aging, tolerances, drift and temperature effect which analog components do, although there are other challenges.
We are going to implement a Finite Impulse Response (FIR) filter which compensates for a digital-to-analog convertors (DAC) sinc roll off. The roll off occurs as most DACs will hold an analog output level until the next sampling point. If you were to look at the output of a DAC (see below) you would see the output waveform is made up from a number pulses.
When a DAC behaves in this manner it is called a zero order hold DAC, looking at the output within the frequency domain we would see the spectrum of the output pulse train multiplied by the Fourier transform of a rectangular pulse. Of course the Fourier transform of a rectangular pulse should be familiar to all engineer as the Sinc function which is the core of the Finite Impulse Response Filter.
What this means is the output of the DAC has an amplitude roll off as the frequency approaches the sampling frequency. The mathematics behind this are
Plotting the above equation clearly demonstrates the roll off.
To create a compensation filter we need to create the inverse function using the following steps
- Calculate the Sinc response for the DAC in the frequency domain
- Calculate the inverse response of the Sinc response
- Perform an Inverse Fast Fourier Transform of the inverse response
- Plot the impulse response from the IFFT
- Obtain the filter coefficients symmetrically around the centre point of the IFFT from the impulse response
Having understood the basics of the theory behind the filter we wish to implement, I need to lay out what we need to do in SDSoC to implement the filter. I intend to use a Digilent PMOD DAC connected to the ZedBoard to output a signal such that we can see the effects of the roll off and the correction filter.
The first thing we need to do is create a new platform definition for the ZedBoard that we can use with SDSoC. This is needed as we want to use the Zynq PS IO peripheral SPI controller to configure and drive the DAC PMOD. To do this we need to route the pins out over the EMIO to a PMOD header on the ZedBoard.
Creating a new platform definition starts as it would for defining any Zynq System within Vivado setting up the hardware as desired. In this case my hardware definition is going to include
- XADC to sample an analog input – this means we can route an analog signal in to the Zynq and back out into the analog domain via the PMOD
- Enable the SPI on the PS side of the Zynq to allow us to drive the DAC PMOD
- Enable three processor clocks and resets from the PS to the PL these will be used by SDSoC and provide for different clocking options when we accelerate our function within SDSoC
- Enable interrupts on the PS such that SDSoC can use these interrupts when it accelerates functions.
Putting all this together means that we have a hardware block diagram as below
Now we have the filter designed and the Vivado hardware completed, in the next article in this series we will import the hardware platform and write the code to drive the DAC and correct for its roll off.