An RTOS-based architecture for Industrial WSN stacks with multiprocessor support -

An RTOS-based architecture for Industrial WSN stacks with multiprocessor support


The industrial wireless sensor network (IWSN) has gathered more and more notice in recent years. Superior reliability, determinism, timeliness, and security are emphasized. Since 2007, three standards, the WirelessHART, ISA100.11a, and WIA-PA, have been released based on the IEEE 802.15.4.

One of the strong similarities they share is the TDMA (time division multiple access) -based media access mechanism. In the TDMA mechanism, all communications among nodes are allocated and limited within corresponding timeslots.

For example, WirelessHART uses 10ms fixed timeslots which allows for maximum packet sizes while still allowing time drift to be technical feasible. ISA100.11a needs flexible time slots to allow for duocast. WIA-PA uses 802.15-4-2006 super-frame with configurable timeslot too.

This is essential to reduce the possibility of collision (and thus increase the communication reliability), and to meet the critical requirement of timing determinism of industrial applications. To do this, all the nodes must be synchronized precisely, i.e. the jitter of synchronization should be much smaller than the length of time slot. Also, the stack designer must guarantee that the node can finish everything within the time slot.

Such timing critical requirement has become one of the primary challenges to design the protocol stacks. Firstly, it is challenging to finish the complicated tasks (packet parsing, encryption, decryption, authentication, etc.) within such a short timeslot by the processor with limited resource (clock frequency, memory, energy supply, etc.). Secondly, the IWSN stacks are often only a part of the timing critical tasks that the device should execute. It is much more difficult to ensure the timing integrity in a complicated multi-task system.

At the same time, the rapidly increasing complexity and other specific requirements of industrial systems have made it necessary to adopt the real time operation system (RTOS) in the IWSN stacks. These requirements include safety, security, availability, support for actuators, system integration, network size, product life cycle, etc.

However, the adoption of RTOS and support of multiprocessor have made it more challenging to guarantee the timing integrity. An optimized architecture is needed, but existing study on this topic is insufficient.

In this paper, we propose an RTOS-based architecture for IWSN stacks with multi-processor support. This architecture offers significant benefits in terms of platform independency, product life cycle, safety and security, system integration, and performance scalability. An implemented WirelessHART stack has proven the feasibility of the proposed architecture in practice and challenges are discussed as well.

The full implementation of the WirelessHART stack for the Field Device is partitioned onto two processors. The radio processor is based on the low cost chip ST32W108CC from ST Microelectronics. It integrates an IEEE802.15.4-compatible transceiver, a 24MHz ARM Coretex- M3 CPU and 16KByte SRAM. Limited by the hardware resources, only lower layers of the stack are allocated in this processor, including the physical layer, data link layer, and the serialization layer.

The application processor is based on the ST32F217ZG from the same vendor. The remaining layers of the stack including the application layer, network layer and serialization layer are allocated in this chip. The application processor has a 120MHz ARM Coretex-M3 CPU, 132KByte on-chip SRAM and 1Mbyte on-chip Flash. On the prototyping board, we add a 512KByte SRAM and a 4MByte Flash on board for the application processor. Many other application modules are integrated in the application processor, too, including field buses and device applications.

Besides the issues related to timing integrity, the extra traffic caused by the inter layer interaction should be evaluated and optimized in the future. In the current prototype, we have noticed that, a huge amount of messages are transmitted between layers in addition to the effective packets.

The primary reason is, in the WirelessHART standard, all the information in lower layers is managed through HART commands from the application layer. This is not an issue if we can use global variables to share all cross layer information. But in the proposed architecture, these global variables have to be avoided to support multi-processor.

Hence, a series of internal messages should be triggered between the application layer and lower layers to execute such a command. Besides the optimization of our architecture, to improve the standards to be more “RTOS and multi-processor friendly” is a feasible strategy. The hands- on experiences gathered from practical implementations should be feedback to the design and update of the standards.

Power consumption is another potential issue. The RTOS and IPC of the proposed architecture may consume extra energy. But the fundamental mechanisms of the protocol itself (e.g. the TDMA and security algorithms) might be the primary obstacle for low power design.

To read this external content in full, download the complete paper from the author online archives at Malardalen University. 

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