Analysis of contemporary ARM and x86 architectures -

Analysis of contemporary ARM and x86 architectures

The question of ISA design and specifically RISC vs. CISC ISA was an important concern in the 1980s and 1990s when chip area and processor design complexity were the primary constraints. It is questionable if the debate was settled in terms of technical issues. Regardless, both flourished commercially through the 1980s and 1990s.

In the past decade, the ARM ISA (a RISC ISA) has dominated mobile and low- power embedded computing domains and the x86 ISA (a CISC ISA) has dominated desktops and servers. Recent trends raise the question of the role of the ISA and make a case for revisiting the RISC vs. CISC question.

First, the computing landscape has quite radically changed from when the previous studies were done. Rather than being exclusively desk- tops and servers, today’s computing landscape is significantly shaped by smartphones and tablets.

Second, while area and chip design complexity were previously the primary constraints, en- ergy and power constraints now dominate.

Third, from a commercial standpoint, both ISAs are appearing in new markets: ARM-based servers for energy efficiency and x86-based mobile and low power devices for higher performance. Thus, the question of whether ISA plays a role in performance, power, or energy efficiency is once again important.

Early ISA studies are instructive, but miss key changes in today’s microprocessors and design constraints that have shifted the ISA’s effect. In this paper, we review previous comparisons in chronological order, and observe that all prior comprehensive ISA studies considering commercially implemented processors focused exclusively on performance.

Today, energy and power are the primary design constraints and the computing landscape is significantly different: growth in tablets and smartphones running ARM (a RISC ISA) is surpassing that of desktops and laptops running x86 (a CISC ISA).

Further, the traditionally low-power ARM ISA is entering the high-performance server market, while the traditionally high-performance x86 ISA is entering the mobile low-power device market. Thus, the question of whether ISA plays an intrinsic role in performance or energy efficiency is becoming important, and we seek to answer this question through a detailed measurement based study on real hardware running real applications.

We have analyzed measurements on the ARM Cortex-A8 and Cortex-A9 and Intel Atom and Sandybridge i7 microprocessors over workloads spanning mobile, desktop, and server computing. Our methodical investigation demonstrates the role of ISA in modern microprocessors’ performance and energy efficiency.

We find that ARM and x86 processors are simply engineering design points optimized for different levels of performance, and there is nothing fundamentally more energy efficient in one ISA class or the other.

While our study shows that RISC and CISC ISA traits are irrelevant to power and performance characteristics of modern cores, ISAs continue to evolve to better support exposing workload-specific semantic information to the execution substrate.

On x86, such changes include the transition to Intel64(larger word sizes, optimized calling conventions and sharedcode support), wider vector extensions like AVX, integer crypto and security extensions (NX), hardware virtualization extensions and, more recently, architectural support for transactions in the form of HLE.

Similarly, the ARM ISA has introduced shorter fixed length instructions for low power targets (Thumb),vector extensions (NEON), DSP and bytecode execution extensions (Jazelle DBX), Trustzone security, and hardware virtualization support.

Thus, while ISA evolution has been continuous,it has focused on enabling specialization and has been largely agnostic of RISC or CISC. Other examples from recent researchinclude extensions to allow the hardware to balance accuracyand reliability with energy efficiency and extensions to use specialized hardware for energy efficiency.

It appears decades of hardware and compiler research has enabled efficient handling of both RISC and CISC ISAs and both are equally positioned for the coming years of energy constrained innovation.

To read more of this external content, download the complete paper from the author online open archives at the University of Wisconsin .

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