Analyzing your design’s high-speed interconnects - Embedded.com

Analyzing your design’s high-speed interconnects

Signal integrity (SI) addresses two key aspects in high-speed digital designs: signal timing and quality. SI analysis aims to ensure signals reach their destination in good condition.

In a system, signals travel through various kinds of interconnections (e.g., from chip to package, package to RF board trace and trace to high-speed connectors), with any electrical impact happening at the source end, along the transmission path or at the receiving end, which affects both signal timing and quality. Connector performance directly affects system performance and reliability. As a result, designing and modeling connectors for multi-gigabit applications is one of the greatest challenges in high-speed digital applications.

When designing high-speed applications, signal transmission quality is a critical factor. At gigabit speeds, high-speed interconnects must be characterized along with the RF board traces. Ever-increasing demand for cleaner signal transmission means that maintaining good signal quality throughout the high-speed interconnects is crucial.

Modern high-speed, multi-pin connectors are required to enable data transmission in systems at a very high rate (~ 5 Gbps). Early design changes based on accurate simulations can be indispensable and worthy investments for interconnect realization. Likewise, use of an accurate electromagnetic (EM) model is highly desirable during the design and implementation stage of high-speed interconnects. To achieve good SI, the designer must not only understand the system in which the connectors will be deployed, but also perform SI analysis of the RF board along with the connectors.

The Hybrid Approach
Over the years, various 3D interconnect simulation techniques have emerged to improve the integrated circuit density and operation speed of multilayer, very large, high-speed board integration designs. However, these techniques often lead to impedance discontinuities that induce SI/power integrity and electromagnetic interference effects when the RF board and connectors are simulated separately.

One way to address this challenge is with hybrid EM simulation. Essentially, with this approach, the connectors (or other 3D components) are integrated with the RF board and simulated together using planar and 3D EM simulation along with a transient solver. The planar simulation is based on a Method of Moment (MoM) solver, while the 3D-EM simulation relies on a Finite Element Method (FEM) solver

To better understand how this hybrid approach works, consider the design and analysis of a serial ATA (SATA) to Universal Serial Bus (USB) data transfer module. Signals originating from the SATA connector go through two pairs of differential lines to a data transfer chip package. From the chip package, signals go to the USB connector through two pairs of differential lines routed on two different layers. The connectors, chip packages and printed circuit boards form electrical paths on which to conduct the SI analysis.

Full-wave numerical analysis of the 3D high-speed and high-density interconnects is used for channel characterization to reduce the crosstalk, reflection and power-distribution noise problems that can cause false signal switching. In such applications, the main cause of impedance discontinuities and crosstalk is the area where the connector is attached to the RF board differential traces. To obtain accurate answers and avoid error-prone, time-consuming measurements, the SI of the complete integrated system must be taken into consideration.

Design and Simulation
Figure 1 illustrates the complete process for modeling the SATA to USB data transfer module. For the purposes of this discussion, the Advanced Design System (ADS) and EMPro software simulation tools were used to characterize the high-speed interconnects, including two connectors and the RF board.

Figure 1. The design flow used to model the SATA to USB data transfer module using ADS and EMPro, a 3D electromagnetic solver with both time- and frequency-domain based EM solvers.

In the first phase of the design process, two high-speed connectors (SATA and USB-3) are designed and simulated using EMPro. From this analysis, important factors from a SI point of view (e.g., impedance matching, reflection, attenuation, impedance mismatch, propagating delay, crosstalk, and alignment shapes of connectors) are analyzed. In order to minimize impedance effects, the connector contact geometry is designed to keep the impedance profile as flat as possible. If the contact spacing is insufficient to reduce crosstalk effect, shielding is applied.

Once designed, the connectors are imported into ADS as a library component. A multilayer SATA to USB-3 data transfer RF board with differential line traces connecting to a chip is then modeled and simulated in ADS layout using a planar EM MoM solver. Next, the SATA and USB connectors are integrated with the RF board module and the complete system simulated using the FEM solver in ADS layout. Finally, post layout SI analyses are carried out using a transient solver to validate waveform quality, timing and crosstalk.The SATA and USB Connectors
SATA interconnect is widely used for faster data rate, smaller form factor and potentially lower cost designs. At higher speeds, SI becomes an important design concern. Due to the faster data transfer rate, a successful interconnect design (e.g., a SATA to PCB interface) becomes crucial to a successful design win. At gigabits speed, the high-speed interconnects must be characterized by S-parameters.

 Figure 2(top) displays the 3D model and pin configuration of the SATA connector in the SATA to USB data transfer module. Four pins are used as two pair of differential signals. Three pins are ground pins. The SATA connector is simulated using a FEM solver to cross check the return loss and insertion loss parameters up to 5 GHz. The simulation result is shown in Figure 2 (bottom ). Note that the return loss is better than -10 dB, while the insertion loss is less that -1.5 dB over the band.

Figure 2. This image depicts (top) a 3D EMPro model and pins of the SATA connector and (bottom) simulated return and insertion loss plots.

USB connectors were developed for serial and parallel data transfers. For a SATA to USB data transfer module, the USB 3.0 standard connector is modeled to specify a maximum transmission speed up to 5 Gbps, which reduces the data transmission time and power consumption. For USB 3.0, the voltage supplied by the low-powered hub ports is 4.45 – 5.25 volts.

The model and pin configuration of the USB 3.0 connector is shown in the Figure 3(top). Note that there are two pairs of differential pins for the transmitter and receiver signals. As is evident from the FEM simulation result in Figure 3(bottom), the return loss is better than -7 dB and the insertion loss is less that -2.5 dB up to 3 GHz.

Figure 3. This image depicts (top) a 3D EMPro models and pins of the USB 3.0 connector and (bottom) simulated return and insertion loss plots.

SI Analysis of the Integrated System
After modeling and optimizing the performance of the USB and SATA connectors, the two models are imported into ADS (with their simulation results) as library components for use in SI analysis. The SATA and USB connectors are integrated are separate components into the layout design of the RF board, which has four pairs of differential channels routed from the data transmit chip to the connectors.

The complete RF board, along with the SATA and USB connectors, is simulated using a FEM solver and then used as a model for transient analysis. You can optimize the complete design by properly characterizing the differential trace width, spacing and routing to obtain good performance in the desired frequency band. Figure 4 shows the system’s return loss and insertion loss for all ports. In this case, the E-field values for the entire system can be very useful in detecting hotspots. These hotspots may be potential sources of EM radiation, which causes serious problems related to EMI compliance. Figure 4c shows the FEM calculated E-field plots for the entire board.

Figure 4a

Figure 4b

Figure 4c

Figure 4a-c. Shown here are the complete RF board simulation results: (a) shows a plot of the return loss (b) shows a plot of the insertion loss and (c) shows the plot of the EM E-Field on the entire board.

Post Layout SI Analysis
During the post-layout SI analysis, the waveform quality, timing and crosstalk for the system-level interface implementations (including connectors and RF board) are validated. Instead of using separate S-parameter blocks of connectors and the RF board for SI analysis, an integrated RF board along with the high-speed SATA and USB connectors are applied for channel simulation. SI analysis on the integrated system provides accurate answers and avoids error-prone and time-consuming measurements.

A channel simulator is used for SI analysis of the complete channel. The channel simulator accounts for crosstalk, encoding, equalization, and other effects of interest to high-speed digital designers. The eye probe component output provides accurate analysis of eye diagram properties including mask compliance, BER contours, density, width, and height. Channel insertion loss is largely dependent on the system impedance profile, impedance mismatch and on the materials used. Crosstalk is created by inductive or capacitive coupling between signal paths. The results of the channel simulation are shown in Figure 5.

Figure 5. These channel simulation results were obtained using a setup with a single TX_Diff component and no crosstalk effect in ADS. A pre-simulated EM model of the RF board with SATA and USB connectors was used. The system was optimized by placing decapacitors between the connectors and the differential trace for the best eye diagram (top) and timing bathtub curve (bottom).

Signal integrity analysis of high-speed digital applications poses a number of challenges, especially when high-speed and high-density connectors (e.g., SATA and USB) are involved. Hybrid EM simulation, which enables simulation of connectors or other 3D components with the complete RF board, now offers a viable way to overcome this challenge.

In the case of the SATA to USB data transfer module, SI analysis results were obtained for the integrated system over a frequency range from 0 to 5 GHz. The eye diagram and bathtub curves were optimized at a data transmission rate of 5 Gbps using decapacitors.

By integrating the system, circuit and EM simulators, the traditionally complex problem of SI analysis was greatly simplified. Not only did the approach yield accurate results, but a reduction in the design cycle time was also realized. This process can be easily leveraged for SI analysis of other complex systems.


Anil Kumar Pandey obtained Master degree in Microwave Engineering from the Institute of Technology. He has 10 years’ experience in RF, Microwave and Antenna Design. Currently he is working in Agilent Technology as Expert R&D Engineer. His working area are Antenna Design for different application, RF & Microwave components design, High speed digital design and Signal Integrity , EMI/EMC analysis, Multi-technology based design, Electronic Design Automation tools and Electromagnetics solvers. Before joining Agilent he worked 4 year as Scientist in Indian Space research organization (ISRO); there he worked on a wide range of projects for communication satellites.

(A version of this article has been previously published on Embedded.com’s sister publication, EDN Magazine. )

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