In design for manufacturing (DFM), PCB design layout engineers can easily overlook key factors that at first glance don’t appear significant. But later on, these factors play a major role during manufacturing and can turn out to be the root cause of poor yields.
When it comes to high-speed PCB designs, above 20 GHz in particular, lack of communication and/or faulty assumptions between PCB designers and the manufacturing team can lead to costly failures during manufacturing. Following are some real-world scenarios in which communication problems have occurred and some tips on how to avoid such problems.
Scenario #1: Reduce pad size to match trace width
In this case, the PCB designer had reduced the pad size to match the trace width. He didn’t think twice about it; it is quite acceptable to do so. Unfortunately, it was reduced so much that this misstep violated IPC and manufacturing rules.
The consequence was a number of issues in manufacturing and in particular, tombstoning occurred, as shown in Figure 1 . Tombstoning is a component defect that occurs at the PCB assembly stage due to the solder’s surface tension during reflow. As a result, one end of the component is detached from a PCB’s copper pad and lifts up vertically, resembling a tombstone.
This situation came about because solder was flowing into the trace because it was the same size as the pad, and there was movement during reflow. The result was a mismatched pad size. Together with other DFM issues, yields were below 60 percent, far below the expected 90 percent.
Other DFM problems included:
- Solder shorts caused by a gang relief mask
- Use of thermal vias caused solder wicking through the barrel
- Insufficient solder mask between two pads
Actually, the PCB designer’s decision to make the trace width as the same size as the pad was indeed correct: in any high-speed signal, discontinuities in impedance are created when a signal’s geometry changes, which in turn changes impedance of a trace. By using the same trace width as the pad size, signal geometry would not change and the amount of discontinuity is reduced when the trace enters the leads of the discrete component pad. In theory this works. However, in practice, manufacturing issues arise when the same size is used for both traces and pads that are too small, resulting in tombstoning and other assembly issues.
Specifically, in this case, the fan out trace is the same size as a pad. Here a ball-grid array (BGA) package is used, with the BGA pads fanned out with a thicker trace. If it’s not a non-solder mask defined (NSMD) pad, the solder flows into the traces for those particular pads, causing a non-uniform pad size forming under the BGA, and subsequently forming cold solder joints or voids, as shown in Figure 2 .
Scenario #2: RF filter problems
In this case, the high-speed design included a specialized RF filter in a three-pin SOP package. Solder mask was not used in between the pins and it was gang relieved, which is a method of defining a solder mask so that the mask is avoided around a group of pins. The result is a set of pins that don’t have solder mask in between. This may be done intentionally or may be a mistake on the part of the PCB designer. The result was solder shorts between the three pads of the filter.
Also, in this case the vias are extremely close to the pads. In fact, half the via encompasses the pad. That only happens if the via’s pad is on top of the component, rather than on the hole. This is a no-no: the hole should never overlap the component’s pad.
In this case, the vias encroached on the component pad, which caused solder to wick through the barrel to cause tombstoning and opens. There are a couple of ways to fan out of the discrete component to avoid this situation. With an eye to design for manufacturing, the best way is to position the via slightly further away from the pad where there is solder mask between the pad and the via hole.
A second way isn’t ideal for fan out. Here the via pad encroaches on the component pad, but not the hole. The result? When the via is tented, there is less likelihood of solder wicking through the barrel. There are two ways to solve this problem. The first option is to put the via directly on top of the pad and have it filled with a non-conductive fill. The second option is to move the via slightly and place solder mask between the hole and the pad.
For this particular high-speed design, a recommended land pattern from the manufacturer was used. The problem is that those recommendations were for low volume prototyping, not for production. A land pattern is one created in the CAD layout tool so that a PCB component can be soldered and makes connections to the PCB by means of an outline of the components as well as pads that will allow pins to be soldered to them.
But when a large number of parts is used on extremely dense boards, it is critically important that the land pattern be modified based on the assembly house’s recommendation.
Then there is the issue of the hole size. It has to be 0.3mm or less, so that the via closes very early in reflow. Ideally, it’s best to have the via shut and plated, but that never happens. For thermal vias, 0.3mm pitch or even finer is all that is necessary to prevent solder from wicking through the barrel.
In our high-speed design example, vias the OEM used measured about 15 mils, but ideally they should be less than 8 mils. Because they were not the correct size, during manufacturing solder was flowing down the barrel due to the larger vias. This caused a suction action on a separate SOP package in the board design that shorted out the peripheral pads (Figure 3 ).
Figure 3: Solder going down the barrel due to the larger vias, causing suction action on a SOP package and resulting in shorts on the peripheral pads. Insufficient solder mask between two pads was a third DFM issue withthis high-speed design. Here, pads were placed extremely closetogether. The result was that the solder mask was too thin, and itpeeled off during the entire process. In turn, that caused solder toflow in a sliver from one pad to another. What had happened was that thediscrete components didn’t have a uniform pad definition due to thatlost sliver, as shown in Figure 4 . Consequently, the component was being shifted from the smaller to the larger pad.
Anotherpad problem in this design had to do with mismatched pad sizes, thistime in the power supply portion of the layout. Very fine 0402 metric(0.4 mm x 0.2 mm) passive device packages were used, which are notrecommended for power layouts. In this situation a Savvy PCB layoutengineer would have used 0603 thick film chip resistors with 1608 metricpackage sizes or maybe 0805 thick film chip resistors with slightlylarger 2012 package sizes. But nothing smaller.
The reason forthis caution is that most power layouts have large copper pours onexternal layers. In this high-speed design example with the 0402packages, one side connecting directly to a copper blob. The other sidejust had a trace and a via. As a result during reflow, that copper blobacted as a heat sink producing a cold solder joint on one side of thepad. To alleviate that issue it is best to create thermal connectionsfrom the pad to the copper. Better yet, use a larger package.
Other examples of sabotaged DFM
Thereare other layout missteps that can sabotage efforts to apply effectiveDFM principles to printed circuit boards. Poorly executed PCB layout cancause fabrication and assembly problems relating to pad definition,component footprint, layer stack-up, material selection, fan out, tracewidth, and trace clearance. For example, poor pad definition can causeopens and shorts at assembly while an inaccurate component footprint cancause non-manufacturability if the component library isn’t correct.
Atlayer stack up, the designer has to make sure the right uniformstack-up is used to avoid warping. He or she also needs to know PCBmaterial requirements to include field requirements. Meanwhile, a keendesign eye has to be placed on fan out. If not performed properly, acidor etch traps occur, thus causing trace damage. Also, if not designedcorrectly, trace widths and clearances are other stages that can lead toshorts.
Fabrication stage problems. At this stage of the PCBdesign and fabrication process Warping occurs when small amounts ofchemical, usually acidic, collect in what are called “acid traps” at theacute angles in a PCB trace. (Figure 5 ). When that chemicalisn’t cleaned up, it can eat away at the traces even after assemblyand/or it can cause intermittent connections while the product is in thefield. Even in small amounts this can even eat away an entire trace ifit is small enough and happens early at the trace width stage or laterat the fan out stage of a layout.
Registration and aspect ratio issues When the PCB has many layers with fine lines and spacing they may causemis-registration of holes and pads. Such registration problems on padsand vias during fabrication can cause multiple shorts, or even totallydestroy the board.
Aspect ratio issues occur at earlyfabrication stages when the PCB goes into computer-aided manufacturing(CAM) and the fab shop finds out the aspect ratio isn’t correct. In thisinstance, hole sizes are extremely small and PCB thickness isconsiderable. Therefore, the fab shop either has major difficulties orisn’t able to fabricate that board.
Copper and solder mask slivers As discussed earlier, copper slivers come about because the PCB hascopper features on external layers. Extremely small, one-ended coppertraces – slivers – can protrude out of the PCB anywhere and any time tocause shorts after assembly.
Solder mask slivers occur whenthere isn’t enough solder mask between pads and vias. There are a numberof causes for this phenomenon, including incorrect placement, incorrectpad definitions, and/or placing exposed vias too close to componentpads.
Stepping through key layout stages
80 percentof PCB layout errors happen due to incorrect part geometry or creation,bad hole definition, inadequate spacing between through holes andsurface mount components, and lack of rework ability around criticalcomponents.
As a result the PCB layout design engineer has tomove gingerly through various stages to avoid such fabrication andassembly problems. For example, BGAs requiring rework may be placed tooclose together. As a result, rework cannot be performed. Also, vias orpads may be too close to the board’s edge, which can cause vias to becut away during routing.
Then there are fiducials, which aremarks on a PCB that provide common measurable points for each and everyassembly step. They permit PCB assembly systems to precisely zero in onthe circuit pattern. Fiducials are used to properly align SMT (surfacemount technology) cameras, which are used during the PCB assembly pickand place phase to identify and help place components in theirrespective locations. Typical positional tolerance of these cameras is+/- 1 mil.
Without fiducial markings to allow the SMT cameras toalign properly, tombstoning occurs because there is mis-registrationbetween the pick-and-place camera and the board. When it comes to finepitch components, the PCB designer needs to make sure there are extrafiducials around those components to aid the SMT camera.
Asnoted earlier, increased spacing is necessary for BGA efficiency. Thereare other issues arising from BGA use such as coefficient of thermalexpansion (CTE) mismatches between the BGA and the boards due toimproperly selected PCB material. If CTE is not comparable, solder jointfatigue can cause opens on the BGA. Also, symmetrical board stack-up iscrucial when using BGAs. Otherwise, solder joint fatigue and boardwarping occur.
Using via-in-pads for BGAs is another area the PCBlayout designer must be careful about. Via-in-pad is widely popular,especially for finer pitch BGAs below 0.75 mm. Compared with dog-bonefan-outs, via-in-pad increases density and allows the use of finer pitchpackages. Also, decoupling capacitors can be placed directly over thevias on the opposite side of the BGA, thus reducing intrinsicinductance.
However, there are drawbacks as well as advantagesto using using via-in-pad. When using via-in-pad, conductive andnon-conductive material is used to fill the vias and then platedover. If the fab house isn’t knowledgeable about this process, a numberof issues can occur. In particular, moisture entrapment is a risk, whichwreaks havoc at assembly. When moisture is trapped, vias and pads canbe popped and dimples can form during reflow that can destroy BGA pads. Apopular approach to avoiding extensive expansion or contraction is touse non-conductive via fillings, which reduces moisture entrapment.
Syed Wasif Ali is an advanced certified designer (CID+) and a layout engineer atNexlogic Technologies, Inc., San Jose, CA. He received his BSEE fromN.E.D. University of Engineering and Technology in Karachi Pakistan. Hehas over 7 years of PCB design experience.