Arasan adds MIPI Conformant CSI-3 Receiver IP Core -

Arasan adds MIPI Conformant CSI-3 Receiver IP Core

Arasan Chip Systems has just announced the addition of new IP cores for the MIPI Alliance CSI-3 Receiver along with a matching Type 1 M-PHY to the company’s expansive MIPI portfolio.

The CSI-3 Receiver and M-PHY’s can be delivered to customers in configurations of 1 to 4 receive lanes. MIPI’s CSI-3 specification is the application layer definition of the latest generation of camera serial interface that utilizes UniPro version 1.41 as its link layer and the M-PHY v. 2.0 as the physical layer. Like CSI-2, the CSI-3 receiver is meant to deliver its image payload to an on-chip Image Signal Processor (ISP).

Compared to CSI-2 with D-PHY, the CSI-3/Unipro/M-PHY combination provides higher bandwidth and lower power consumption per bit transferred from a camera module or bridge chip to a receiver in a mobile applications processor.

Arasan offers UniPro v. 1.41 as part of the CSI-3 Receiver IP, which is deliverable in source RTL form with accompanying verification IP targeted for rapid design integration.

Arasan’s Type 1 M-PHY’s, which are licensed separately, are designed to be compatible with the CSI-3/UniPro PHY Adapter layer, with flexibility in data bus widths across the RMMI interface.

Arasan’s MIPI CSI-3 Receiver IP Core is available immediately for licensing, including Verilog HDL of the IP Core, Verification IP, synthesis scripts, and documentation. The corresponding M-PHY IP is available as a hard macro targeted to any process node, along with all the customer required support files and documentation.

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