ARC and Ashling cooperate to raise RISC development support -

ARC and Ashling cooperate to raise RISC development support

Ashling Microsystems is working with ACR International to provide complete debug solutions for systems based on the ARC-tangent user-customizable 32-bit RISC/DSP microprocessor core and aid the development of configurable system on chips.

The Ashling Vitra, Genia and Opella emulators provide users with run-time control and trace tools for ARC's reconfigurable cores.

The Ashling tools are designed to ensure that users of the ARCtangent embedded RISC/DSP core can access a development and debug toolset for both pre-first-silicon and post-first-silicon design.

“This new cooperation means that users of ARC's unique reconfigurable RISC architecture can utilize the Ashling toolset to rapidly and reliably design, integrate, debug and validate their products,” said John Murphy, CEO of Ashling Microsystems.

“Ashling has a long track record of success in development tools and we are pleased that they are quickly rolling out a range of tools for SoC developments based on our embedded RISC/DSP architecture,” said Mike Gulett, president and chief executive of ARC International. The complete toolset combines ARC's proprietary Metaware tools and the Ashling developed products. The full ARC tools environment includes ARC's MetaWare High C/C++Embedded Development Tool Suite; the MetaWare SeeCode' Debugger; a JTAG emulator and a Real-time Trace system from Ashling.

Published in Embedded Systems (Europe) November 2002

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