Architecture readied for embedded processor enhancements - Embedded.com

Architecture readied for embedded processor enhancements

STMicroelectronics NV is set to expand its Structured Processor Enhanced Architecture (SPEAr) family of embedded microprocessors with the use of an advanced symmetrical multiprocessor architecture.

ST first introduced the SPEAr family in 2005 and as recently as February 2010 added four variants of the SPEAr300 and SPEAr600 lines and in March demonstrated system solution for Laser printers based on the SPEAr600.

SPEAr1300 is the latest addition and uses dual ARM Cortex-A9 processors with a DDR3 memory interface and is manufactured in ST’s low-power 55nm HCMOS (high-speed CMOS) process technology. Initial sampling has already started to early adopters.

The dual ARM Cortex-A9 processors support fully symmetrical operation, at speeds up to 600MHz/core for 3000 DMIPS equivalent.

The SPEAr1300 makes use of ST’s Network-on-Chip technology for internal peripheral interconnect, assuring support for multiple different traffic profiles, while maximizing data throughput.

The availability of integrated DDR3 memory controller and a full set of connectivity peripherals like PCIe, SATA, USB and Ethernet make the SPEAr1300 suitable for high-performance applications including networking, thin client, videoconferencing, NAS (Network-Attached Storage), computer peripherals, and factory automation.

Embedded microprocessors from the new SPEAr1300 product line will be announced over the next few months.

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