ARM beefs up 64-bit support with new CoreLink IP -

ARM beefs up 64-bit support with new CoreLink IP


ARM Holdings plc this week added two elements to its family of CoreLink system IP family aimed at systems chips for use in 64-bit network router and server applications.

The two additions are the CCN-504 cache coherent network chip with integrated level-3 capability and the DMC-520 dynamic memory controller that has been designed and optimized to work with CCN-504. They are configured to support the Cortex-A15 processor and the ARMv8 64-bit instruction set architecture. Initial designs are currently targeting 28-nm CMOS process technologies but 20-nm designs are in the works.

The CCN-504 I extends the cache coherent multicore capability up to four, quad-core CPUs (16 cores) compared to the previous generation CCI-400, which supported up to a maximum of 8 cores with cache coherency. The CCN-504 also supports heterogeneous computing through additional CPUs, DSPs and accelerators accessed through a non-coherent network interconnect.

The IP block can deliver up to one terabit per second of bandwidth via a 128-bit wide bus channel and provides a level-3 cache configurable between 8-Mbytes and 16-Mbytes. The CCN is targeted by ARM for use in SoC designs in enterprise-oriented network infrastructure and servers and server-type functions merging with communications networks.

Based on the AMBA 4 ACE specification released a year ago, the CNN in addition supports dynamic frequency and voltage scaling (DFVS) in CPU clusters including big-little processor clusters, allowing improved energy-efficiency and lower latency than software coherency. A snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.

CCN-504 and DMC-520 used in a typical SoC design. Source: ARM

While the CCN itself is for the most part operates in a single clock domain that runs in the gigahertz range, it is also possible to voltage-scale the interconnect fabric. The CCN-504 logic can be switched off and a keep-alive voltage used to maintain the level-3 SRAM cache ready for power up.

The DMC-520 is a dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. It supports DDR3, DDR3L and DDR4 DRAM and is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan DDR4/3 PHY IP planned for introduction in 2013.

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