Arm, Cadence Design Systems and Xilinx announced the delivery of a new development platform, silicon-proven on TSMC’s 7nm FinFET process technology, for next-generation cloud-to-edge infrastructure based on the new Arm Neoverse N1 platform. The Neoverse N1 System Development Platform is also the industry’s first 7nm infrastructure development platform enabling asymmetrical compute acceleration via the CCIX interconnect architecture and is available to hardware and software developers for hardware prototyping, software development, system validation, andperformance profiling/tuning.
The SDP includes a Neoverse N1-based SoC with an operating frequency of up to 3GHz, full-sized caches and generous amounts of memory bandwidth with the latest optimized system IP. The robustness of the SDP is ideal for development, debug, performance optimization and workload analysis on a wide range of applications including those for machine learning (ML), artificial intelligence) and data analytics.
The Neoverse N1 SDP was developed jointly by Arm, Cadence and Xilinx on TSMC’s process technology, and includes Cadence IP for CCIX, PCI Express Gen 4 and DDR4 PHY IP. The SDP was implemented and verified using a full Cadence tool flow in TSMC’s 7nm FinFET process technology, the industry’s first and leading 7nm process technology in volume production, and provides connectivity to Xilinx Virtex UltraScale+ FPGAs over the CCIX chip-to-chip coherent interconnect protocol via the Xilinx Alveo U280 CCIX accelerator card. For customers with intense compute workloads, CCIX offers a significant accelerator usability improvementas well as improved data center performance/efficiency, lowering the barrier to entry into existing server infrastructure systems and improving the total cost of ownership of acceleration systems.