ARM debuts multiprocessing core - Embedded.com

ARM debuts multiprocessing core

The MPCore synthesizable multiprocessor is a new form of licensable processor developed by ARM as part of its ongoing partnership with NEC Electronics. Based on the ARMv6 architecture, it can be configured to contain between one and four processors delivering up to 2600 Dhrystone MIPS of performance.  The MPCore multiprocessor implements Adaptive Shutdown technology and the ARM Intelligent Energy Manager technology to reduce power consumption by up to 85percent. NEC will use the configurable ARM processor in high-performance, low-power products across the consumer electronics, automotive and mobile markets. 

The ARM multiprocessor solution has been designed to deliver improved performance at lower frequencies than comparable single processor solutions, enabling cost savings in system design.

Multiprocessing is suitable for demanding applications executing multiple tasks at the same time such as consumer entertainment and convergence devices in the home and car. Examples include a set-top-box recording several TV channels while sharing home movies across the Internet, and an in-car navigation system delivering simultaneous back-seat video gaming.

The MPCore multiprocessor supports up to four-way cache coherent symmetric multiprocessing (SMP), up to four-way asymmetric multiprocessing (AMP), or any combination of both. 

This flexibility provides increased throughput and system responsiveness, with full portability of existing applications and scalable performance for multithreaded applications. The ability to support multiple workloads addresses the needs of networking devices to process more packet streams and higher data throughput.The MPCore multiprocessor supports both SMP and AMP software models, and supports a broad range of operating systems and application software.

The MPCore multiprocessor supports the ARMv6 architecture, with SIMD media extensions for next-generation rich multimedia and convergent devices and ARM Jazelle Java acceleration. 

The MPCore multiprocessor implements between one and four processors with cache coherency using a modified MESI protocol. It also features configurable level 1 caches, 64-bit AMBA AXI interfaces, vector floating-point coprocessors and programmable interrupt distribution. The processor supports Adaptive Shutdown of unused processors to give dynamic power consumption as low as 0.57mW/MHz from a generic 130nm process excluding cache. The ARM Intelligent Energy Manager technology can further reduce consumption by dynamically predicting the required performance and lowering the voltage and frequency.

The MPCore multiprocessor enables system designers to view the core as a single ‘uniprocessor’, simplifying development and reducing time-to-market.

The MPCore multiprocessor is available for licensing from ARM now with first silicon expected Q2 2005. An evaluation system for the MPCore multiprocessor with Linux 2.6 OS and development tools is available to enable early software development for MPCore multiprocessor designs.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.