SAN JOSE, Calif. — The big news at Arm Techcon this year is that Arm is opening up its instruction set to customers’ customized instructions for Cortex M cores.
Arm CEO Simon Segars (Image: Kevin Krewell)
Arm CEO Simon Segars announced the changes in his opening keynote at Arm TechCon. After decades of tight control over the Arm instruction set architecture (ISA), Arm has finally decided that it can allow its licensees to build their own custom instructions, which are often useful to accelerate specialized workloads.
In the past, Arm resisted this move, intently focusing on the maintenance of a consistent programming model. Meanwhile, a host of other intellectual property (IP) companies made a good business out of customizable instruction sets. They include Tensilica (now part of Cadence) and ARC (now part of Synopsys). The venerable MIPS instruction set also supported user-defined instructions.
And now, with the rise of the open-source RISC-V ISA and its user configurability, it appears that Arm has finally relented and opened its instruction set for customized instructions. This new customizable capability and the Arm Flexible Access licensing program do address two main issues that are viewed by many as factors driving its customers to RISC-V.
First on Cortex M, then Cortex-R
This initial foray into customizable instructions will be made available for the Cortex-M cores. The move is designed mostly for microcontrollers and controller cores inside larger SoCs.
The first Cortex-M part to support customizable instructions is the Cortex-M33. Future Cortex-M cores will support this level of customization.
The other good news is that Arm is not charging extra for the ability to customize new instructions for the Cortex M33. Arm Fellow Peter Greenhalgh later in the conference indicated that Arm will offer customizable instruction support for the real-time Cortex-R cores and may eventually offer this feature on the Cortex-A cores used in application processors.
Adding custom instructions to Cortex-R can be very helpful for real time control applications. They can use specialized instructions to speed specialized calculations or data movement. When and how Arm will add custom instruction support to the Cortex-A cores, deployed in mainstream applications such as smartphones and servers, is far more complicated and the company did not officially commit to doing so.
Maintaining reliability and security
Arm has designed its toolchain to support these new user instructions in Armv8-M instruction set and still maintain the reliability and verification that users have always expected from Arm. To maintain core security, the company has made the new capability compatible with Arm TrustZone where the custom instructions will be monitored.
While Arm is late to the custom instructions party, the company is responding to customers who have been asking for this ability for some time. There are cases where even one specialized instruction can offer significant gains in performance and efficiency, with fewer clock cycles, and a reduction in total energy. The new instructions use the same registers, but requires additional logic, which requires an investment in additional die area and design time.
The new instructions are interleaved with standard Arm instructions. To avoid software fragmentation and maintain a coherent software development environment, Arm expects customers to use the custom instructions mostly in called library functions.
The initial applications Arm expects to see customers using custom instructions on the Cortex-M33 are storage controllers and modems. The new capability will become available for the Cortex-M33 in 2020 as a free upgrade.
For Cortex-A cores, Arm is still a long way from offering any customizable instructions, but it is preparing new instructions and security extensions for the future. The company unveiled the code name for the next generation of Cortex-A cores after Hercules: it’s called Matterhorn. That processor core will add new instructions to accelerate matrix multiplies, commonly used in machine learning neural networks.
Arm expects the new Matterhorn core will offer a 10x improvement on General Matrix Multiply (GEMM) calculations for neural networks. Arm will also be adding new security measures throughout the CPU core and caches. These security extensions will be able to control pointer authorization, and offer branch target identifiers and memory tagging extensions. Arm plans to offer another Platform Security Architecture (PSA) EL2 compliance with these new capabilities.
Reduced licensing fee
Earlier in July, the company announced a new licensing plan that provides customers access to some of its most popular IP at a reduced price. Customers can do so without the need to sign a licensing agreement until a chip is taped-out. Under Arm Flexible Access program, customers pay only $75,000 per year for a single chip and $200,000 for an unlimited number of chips. This program lowers the financial barrier to getting started using Arm cores.
These changes are viewed as Arm’s competitive response to RISC-V. But Arm is taking a step further to make a fundamental change to its own corporate culture.
Arm has undergone a cultural shift and embracing a more collaborative model with its ecosystem. As another example of those changes, the company opened up the governance of the open-source Mbed OS to its silicon partners. This will allow those partners to more directly influence future developments of Mbed. Presently, Analog Devices, Cypress, Maxim Integrated, Nuvoton, NXP, Renesas, Realtek, Samsung, Silicon Labs and u-blox, are active participants.
Arm is responding to market and customer demands in a way it has never done before. There are still existential threats to the company, like RISC-V. But the company’s IP has shipped in 150 billion chips to date and it expects to double that number in two years. Arm is a critical IP supplier to vast majority of the devices shipped every year and it is making crucial changes to keep up with changing market and customer demands.
Kevin Krewell is Principal Analyst at Tirias Research. Previously, he was a Senior Analyst at The Linley Group and a Senior Editor of Microprocessor Report. He has more than 25 years of industry experience in both engineering and marketing positions including Director of Strategic Marketing at Nvidia and Director of Technical Marketing at Raza Microelectronics (now part of Broadcom). He earned a BS in electrical engineering from Manhattan College and holds an MBA from Adelphi University.
>> This article was originally published on our sister site, EE Times: “Arm Responds to RISC-V, and More.”