As an IP provider, ARM faces interesting challenges in ensuring licensees and customers can address low power product designand implementation in consumer markets where responsiveperformance must be traded off against active and standby power and battery life.
In the market areas where ARM is focused the success metrics for end products are qualified in terms of time-to- market, volume manufacturability, and end-user active and standby experience. This is predicated upon using industry standard EDA tools and design-flows wherever possible for the hardware design, implementation and verification of the SoC component of the product, and the operating system software layers that support the user interface and applications software.
The ARM business model is built on the design and licensing of IP cores and supporting interconnect and sub-systems, typically technology independent and with levels of parameterization and configuration.
But this grew out of experience in the 1990’s of designing and delivering technology-specific ‘hardened’ CPU IP cores where full-custom design techniques could be used and the macro-cell was delivered pre-verified and with known (characterized) performance, power and area.
The main challenge back then was developing the model abstractions that would allow the physical, functional (simulation), timing, power and test views to work with portability across a wide range of customer design flows and vendor-specific EDA tools.
Investment was also put into interconnect standardization to support uniform memory- mapped access to, and hardware debug of, user-developed peripherals and sub-systems.
The lessons learned from hard-macrocell deployment have proved invaluable to building the know-how to deliver synthesizable (‘soft’) IP cores. A number of years working with EDA companies to develop the implementation and verification support that enables customers to parameterize, build, verify and characterize SoC IP themselves is bearing fruit in allowing multiple customers to develop and optimize designs in parallel.
Academic research on mitigating dynamic and static power, such as Dynamic Voltage and Frequency Scaling and Power-Gating respectively is well understood and exploited in full-custom and ‘expert’ design flows for standard products and integrated circuits.
However, enabling such techniques to be deployed successfully by SoC design teams that need to rely on standard-cell design flows and industry standard test and sign-off tools has required significant work with EDA companies and standards committees.
The next level challenge is then at the system design level to ensure optimal control of the hardware added for active and standby power management. This paper explores the “energy management stack” and enabling the eco-system that supports ARM partners and customers to address power and energy efficiency across a wide range of consumer products.
To read this external content in full, download the complete paper from the online open archives at Pensylvania State University.