ARM releases power-optimized dual-core Cortex-A15 hard macro - Embedded.com

ARM releases power-optimized dual-core Cortex-A15 hard macro

Looking to meet the demands of company licensees who continue to want more performance at lower power for use in mobile devices, ARM Ltd.  has a hard macro version of its Cortex-A15 processor.

Demonstrated at the Design Automation Conference in Austin, Texas, the power efficient Cortex-A15 is designed to provide substantial power efficiency but at the same time deliver up to 10,000 DMIPS within a constrained mobile power envelope.

It combines not only the Cortex processor IP, but as well Artisan physical IP, CoreLink systems IP and uses TSMC’s 28nm HPM process.

This low leakage implementation hard macro features integrated NEON SIMD technology and a floating point engine, and includes a 1MB level 2 cache to deliver an extremely competitive balance of performance and power.

This dual-core hard macro not only uses the ARM Artisan 9-track libraries but also incorporates ARM POP technology for the Cortex-A15 on TSMC’s 28nm HPM process.

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