ARM wrestling puts core, MCU on card - Embedded.com

ARM wrestling puts core, MCU on card

SUNNYVALE, Calif. — A pair of 32-bit ARM-based embedded processors will let designers wrestle with a tough choice—take advantage of an off-the-shelf ARM 9E based solution from STMicroelectronics or design their own high-performance solution with the latest Cortex-R4 ARM core from ARM Ltd.

The STR910F family from STMicroelectronics combines Ethernet connectivity, an ARM9E processor core, and large embedded SRAM and flash memories along with a large assortment of I/O support functions. The ARM966E-STM core in the STR910F series delivers better performance than previous ARM7-based solutions—it accesses its instruction and data memories using two separate internal buses, thus enabling simultaneous access of both code and data, said Mark Rootz, marketing manager for ARM9-based products in the Microcontroller Division at STMicroelectronics.

“Each of these memories is attached to the core through a highly optimized tightly-coupled memory (TCM) interface for rapid access. The STR910F exploits this architecture by placing a high-speed burst flash memory on the instruction TCM, and a zero-latency SRAM on the data TCM,” explained Rootz. “The result is 96 MIPS peak code execution at 96 MHz (the highest peak performance for general-purpose Flash ARM-based MCUs), and extremely efficient data movement between the CPU core and SRAM.”

By contrast, the ARM7TDMI CPU core shares a single bus for access to its instruction and data memories, making simultaneous access impossible. Both the ARM7TDMI and ARM966E-S cores execute the standard ARM and Thumb instruction sets.

The STR910F was given large memories to support the use of RTOS and TCP/IP stacks, in addition to complex control applications, said Rootz. SRAM sizes range up to 96 kbytes, the largest SRAM of all general-purpose ARM-based flash MCUs and ideal for larger packet buffers enabling faster serial communications.

For higher performance, the Cortex-R4 processor core leverages an advanced microarchitecture with dual instruction issue to deliver more than 600 Dhrystone MIPS when implemented in a performance-optimized 90-nm process flow (based upon the ARM Artisan Advantage library). The core runs the enhanced Thumb-2 instruction set and can trim cost and power consumption for system developers, said John Cornish, the vice president of marketing of the Processor Div. at ARM.

“The core occupies less than 1 mm(superscript 2) and consumes less than 0.27 mW/MHz, when fabricated in an area-optimized 90-nm process flow,” stated Cornish. “This latest member of the Cortex processor family gives chip designers a high-performance processor for use in 3G phones, hard-disk drives, imaging and automotive systems to name a few applications”.

The Cortex-R4 employs an eight-stage pipeline vs the five-stage pipeline in the ARM9E. Additionally, the latter stages of the device’s pipeline were split into four parallel pipelines, each able to handle different instruction types to speed processing. By contrast, the 9E core pipeline can only process a single instruction in each stage.

The ARM Cortex-R4 processor is available for licensing now, along with the Instruction Set Simulator (ISS) and RealView Development Suite tools environment. ST’s STR910F family comprises six devices in 80 or 128-lead lead-free packages priced from $6.99 for the STR910FM32X6.

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