Asymmetric multiprocessing boosts subsystem isolation - Embedded.com

Asymmetric multiprocessing boosts subsystem isolation

The Diamondback APM86392 and APM86391 are the latest additions to the Applied Micro Circuits Corp. PacketPro family of multi-core embedded processing devices.

The devices use asymmetric multiprocessing (AMP) to enable two or more independent subsystems to operate concurrently with effective isolation on a single chip. This can improve application performance and reliability and is also designed to provide an easier migration to multicore designs with  flexibility for a range of embedded applications in networking, storage, printing, imaging, and multimedia access systems.

Many multi-core processors force software engineers to dedicate one of the cores as a master to control the operations of the other slave cores. The PacketPro family uses AppliedMicro's Scalable Lightweight Intelligent Management processor (SLIMpro) subsystem, to implement AMP on APM8639x processors without dedicating one of the cores as a master.

This enables completely separate and isolated partitions on a single chip, each with independent operating systems, applications, software, processing bandwidth, I/O and cache. Each subsystem is decoupled from other subsystems during software updates, crashes, rebooting, peak performance demands or other events that can interrupt continuous operations.

In the traditional master-slave design a system fail can require a complete reboot. Both subsystems would have to be taken down to reboot one operating system due to dependencies from shared cache memory and other resources.The PacketPro technology allows the decoupling of cores without interruption or impact of other subsystems running on the same embedded SoC device only one core has to be restarted.  So each processor has separate and virtualized access to processor resources so that one subsystem can continue operation even if any of the other ones becomes inoperative.

The AMP approach is designed to aid developers who are migrating from single-core to multi-core designs by allowing consolidation of several applications onto one SoC without the re-engineering that typically accompanies porting of software to a multi-core environment. This reduces overall development time and costs.

The SLIMpro subsystem also manages multiple power islands on the SoC to meet low-power, energy efficiency requirements.

The non-blocking architecture of PacketPro is arbitrated by queue management and traffic management so that each individual application should not suffer from a lack of processing resources

AppliedMicro's Diamondback APM86391 single core devices and APM86292 dual-core processors feature PowerPC 465 processing cores operating at up to 1.0GHz with floating point units, 32 KB I- and 32KB D-cache, 256 KB L2 cache per processor, 32-bit DDR at 1066 Mbps DDR3 memory controller with optional ECC.


APM86292 dual-core processor

High-speed interfaces consist of GE ports with in-line classification, security and TCP/IP offload, three single lane PCI-e Gen 2, two USB 2.0 host with integrated PHYs, one USB 2.0 OTG with integrated PHY, and one SATA 2.0 ports.

The Serengeti evaluation platform is available now running up to 1.0GHz and exposes all interfaces available on the SoC. The PacketPro family is supported by an ecosystem of third-party suppliers such as WindRiver, VxWorks, Free BSD, Enea, NetBSD and others.

Samples quantities of AppliedMicro's APM8639x SoCs are available now with production quantities expected later this year.

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