San Jose, Ca. – Atmel Corp.this week said it is going into volume production on anew category of customizable metal programmable 32-bit ARM-basedmicrocontrollers it calls Customizable Atmel Processors (CAP).
Not quite standard products, not quite an FPGAs, nor a gatearray/standard cell ASICs, the company claims the new ARM7 andARM9-based CAP devices have features and capabilities of all of thesealternatives, but fit into a price and performance niche that none ofthese canadapt to quite as easily, if at all.
As if that were not enough, unlike FPGA and ASIC vendors who requirethat customers make their own arrangements with ARM Ltd., there are nolicense fees or royalties charged for the ARM cores implemented by theuser in the CAP devices, with the cost absorbed by Atmel.
According to Jay Johnson, director of ASIC marketing at
“The number of designs with signal processing is exploding,” he said.” So far, designers have been limited to three options foralgorithmically complex designs: a DSP processor, an FPGA or a customASIC. “FPGAs have made significant inroads into this market becausethey implement DSP functions faster than DSP processors and do notrequire the huge volumes and NREs associated with ASICs.
However, FPGAs have notoriously high power consumption and theirperformance is a fraction of that of custom ICs.<>Like all Atmel's 32-bit microcontrollers, AT91CAP MCUs includeanAtmel processor core, a variety of peripherals (each with its own DMA),and multiple high-speed busses.
Metal Programmable Cell Fabric atthe core
But what makes the new customizable processors unique is a metalprogrammable block (MP block) with up to two-million FPGA-equivalentgates that can be used to implement any of the following: 1) DSPalgorithms or other IP commonly implemented in FPGAs, 2) one or moreadditional processor cores or 3) additional peripherals not currentlyavailable on Atmel's standard product ARM7- and ARM9-based MCU families.
The result of a two- tothree-year- development effort, the metal programmable logicblock is an outgrowth of a technique originally developed by Atmel'sstandard cell design group to allow company designers to quicklydevelop standard products for fast growing and developing marketsegments.
“What we saw as we proceeded was that there was an even greateropportunity if we could develop a methodology that would allowdevelopers to quickly generate variations of standard productsoptimized for their particular needs,” said Johnson, “without thecost, die size or performance burden that FPGAs imposed.”
Where the original standard cell process used a two layermetallization, the
Incorporating a compact 8-transistor core cell that can beconfigured into more than 400 different functional elements using acustom-developed library, Johnson said the MPCF's efficient cellrouting and additional metal layers provide much higher transistor andplacement utilization than alternative technologies.
“With routed gate densities nearly identical to those of standardcells ASICS, in the same process technology, MPCF technology makes CAPMCUs 30% to 50% less expensive than the comparable MCU-PLUS-FPGAsolution are even cost-competitive with standard cell ASICs,” he said.
By integrating a system's unique IP and glue logic on-chip with theMCU, said Johnson, the on- and off-chip delays associated withcomparable FPGA implementations is eliminated with the logic capable ofbeing run at full bus speed with zero wait states. “The MP block iscapable of clock rates of 400 MHz or more, potentially increasingperformance of FPGA logic implemented in the MP block by 8 times,” hesaid.
To allow developers the maximum of flexibility in their use of themetal programmable logic block, the AT91CAP-enabled MCUs have amultilayer bus matrix with multiple bus masters dedicated to the MPblock that eliminate bus contention and maximize on-chip bandwidth.
For example, one of the new devices in the family, the ARM7-basedAT91CAP7, has a six-layer bus with four bus masters dedicated to the MPblock for maximum on-chip bandwidth of 19.2 Gbps. The other device, theARM9-based AT91CAP9, has an 12 layer bus with three bus mastersdedicated to the MP block for a 38.4 Gbps maximum on-chip bandwidth.
MPCF-based CAPs are multicore-able
The metal programmable approach is also very multi-core friendly,especially if the developer has a design that involves both a standardARM configuration with some customized core variation. The MP block onthe CAP9 devices, said Johnson, was designed to enable theimplementation of a second ARM926EJ-S core with caches.
“Alternatively, it can also implement an AVR32 core or multiple8-bit cores, allowing designs with multiple MCUs to be completelyintegrated on a single system-on-chip (SoC),” he said. “For example,sensor-rich industrial control systems frequently require 8-bit MCUsfor each sensor in the system.
“Multiple 8-bit MCUs can be integrated on a CAP-enabled device,reducing cost, power consumption and system complexity. Bus mastercontrols and DMA access can be provided between the MP block and thesystem bus to provide maximum connectivity for the additionalprocessors.”
Based on the ARM7TDMI processor core, the AT91CAP7S MCUs come withcustomizable logic equivalent to approximately 28K or 50K FPGA LUTs or250K or 450K routable ASIC gates. The ARM9-based AT91CAP9S integrates a200 MHz ARM926EJ-S core with 16 KBytes each of program and data cache,and customizable logic equivalent to approximately 28K or 56K FPGALUT's (250K or 500K routable ASIC gates).
Any existing ARM7/9 -plus-FPGA design can be migrated to a AT91CAPdevice, said Johnson. “Even with the high degree of customizationin a AT91CAP device, the NRE is only $150,000 including mask,engineering charges, and prototypes,” he said.