Santa Cruz, Calif. — As a functional-verification consultant, Steve Burchfiel once had to construct a verification plan from hundreds of pages of continually changing specifications….
Santa Cruz, Calif. — Verification startup Jeda Technologies Inc. believes so strongly in SystemC that it shelved its own Jeda verification language. The result is…
Santa Cruz, Calif. — It's one thing to design individual blocks for large systems-on-chip and another to tie them together into a working device. Sierra…
Santa Cruz, Calif. — One of the most common ways to use SystemC is to write transaction-level models that greatly speed the verification process. These…
Santa Cruz, Calif. Asynchronous logic can have power and performance benefits, but asynchronous design tools are generally unavailable. U.K. startup Silistix Ltd. plans to…
Santa Cruz, Calif. Matlab users who want to speed verification or support system-level design with C-language models typically have to manually convert Matlab models…
Santa Cruz, Calif. After working in labs designing fault-tolerant flight control systems, Dave McFarland came to realize that there's no good way to specify…
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