Avoiding embedded PCB design defects - Embedded.com

Avoiding embedded PCB design defects


A number of different solder defects and associated failures in embedded designs are becoming more prevalent due to smaller printed circuit boards (PCBs) as well as shrinking ball size and pitch of ball-grid array (BGA), chip-scale (CSP), and quad-flat no-lead (QFN) packaging.

For example, today’s highly advanced BGA packages are fitted with tiny balls ranging from 0.15 to 0.25 millimeter (mm) in size, according to Institute of Printed Circuits (IPC) literature. BGA ball pitch, on the other hand, ranges from a standard 0.8 to a more advanced 0.25 mm pitch. Pitch is defined as the spacing between the center of one BGA ball to the center of the next one. As a result, there’s little area left for the soldering process.

If you haven’t already, it’s a good idea to add the following terms to your embedded design vocabulary and take them under consideration for your next designs:

  • Shorts
  • Opens
  • Bridging
  • Tombstoning
  • Cracked ball
  • Head-on-pillow
  • BGA intermittent connections

The following conditions increase the probability of incurring greater numbers of these defects:

  • Poor solder paste deposition
  • Poor stencil quality
  • Less than perfect thermal profile
  • Inadequate assembly and inspection systems,
  • Out-of-date assembly floor personnel training, and
  • Lack of collaboration between embedded designer and assembly/manufacturing engineering.

Plus, printed circuit boards (PCBs) are getting considerably smaller and tend to be loaded with greater numbers of smaller device packaging like micro ball-grid arrays (BGAs) and chip-scale packaging (CSP), as well as smaller passives like 01005, which can barely be seen by the naked eye. That means accurate solder deposition is facing new challenges.

Figure 1: Shorts defined as defects occur when placing too much solder paste on a BGA ball.

Let’s start with shorts defined as defects that occur when placing too much solder paste on a BGA ball, as shown in Figure 1 . Conversely, if enough paste isn’t applied, a cold solder joint results. An ‘open’, also known on the assembly floor as a non-collapsed ball issue (Figure 2 ), results from insufficient heat applied during the reflow process.

Figure 2: ‘Opens’ or non-collapsed balls result from insufficient heat applied during reflow process

Figure 3 shows the bridging defect that occurs when the thermal profile is too hot.

Figure 3: Bridging defect occurs when the thermal profile is too hot.

‘Tombstoning’ (Figure 4 ) is created due to the solder’s surface tension during reflow. As a result, one end of the component is detached from a PCB’s copper pad and vertically lifts up, resembling a tombstone.

Figure 4: ‘Tombstoning’ is created due to the solder’s surface tension during reflow.

A micro hairline crack on a BGA ball (Figure 5 ) is due to solder-joint fatigue damage caused by thermo-mechanical and shock stresses.

Figure 5: Micro hairline crack on BGA ball is due to solder-joint fatigue damage caused by thermo-mechanical and shock stresses.

Figure 6 shows the ‘head-on-pillow’ defect. In this case, the deposited solder paste only wets the pad. However, it doesn’t fully wet the ball. As a result, the solder joint has a sufficient enough connection for electrical integrity, but doesn’t have enough mechanical strength, thus making it a candidate for a failure in the field.

Figure 6: ‘Head-on-pillow’ defect is caused when deposited solder paste only wets the pad but doesn’t fully wet the ball. BGA intermittent connections
Last on the list of top sevendefects are the prevalent and highly elusive BGA intermittentconnections (BICs). A less than perfect thermal profile used tocalibrate reflow soldering can be the main reason for BIC creation andis the basis for most embedded design defects. When all the zones of athermal profile are dialed in properly, the result is a perfect reflow.

Severalfactors determine thermal profile accuracy. These include PCB layers,thickness, and dimensions, as well as number of planes, PCB materialtype, and component types. A poorly defined profile produces suchdefects as those described above. Moreover, a BIC easily occurs if a PCBisn’t reflowed to a long-enough pre-soaking or to the requiredpeak-time cycles.

At times, manufacturer specifications areoverlooked, and an insufficient flux activity is dispensed at BGAlocations on the PCB. In other cases, the thermal profile isn’taccurate, thereby resulting in BGA balls not properly collapsed. Here,the objective is to apply enough heat to a BGA’s middle section so thatan even collapse of all the BGA balls is created.

Two otherexamples of BIC causes are un-tented vias and poorly defined stencilapertures. At times, inexperienced embedded designers place vias next toBGA pads or around BGA peripheries.  Consequently, this design misstepdisrupts perfect reflow soldering. Solder is sucked into these viasduring reflow rather than being applied to the BGA balls. This problemoccurs when vias aren’t properly masked or tented and results in a BGAwith voids. Figure 7 shows the result of an inadequate reflowwhen either not enough paste is dispensed on the BGA’s balls ortemperature ranges in the reflow oven aren’t correctly dialed in.

Figure7: BGA with voids result from an inadequate reflow when either notenough paste is dispensed on the BGA’s balls or temperature ranges inthe reflow oven aren’t correctly dialed in.

Conversely,experienced embedded designers know to mask or tent BGA vias at thedesign and layout level. Even when this step is omitted, adesign-for-manufacture (DFM) check mapped out at the planning stages orCAM level can catch this issue. Otherwise, reflow becomes a majorchallenge and undetected vias with solder paste traces can cause highlyevasive BGA intermittent connections. Also, if stencil apertures aren’tdesigned properly, too much or too little solder paste is dispensed atcertain BGA solder points, thus creating BICs.

Collaborating with assembly and manufacturing
Theembedded designer can easily blame assembly for producing thesedefects, and a number of inexperienced ones do. However, veteranembedded designers, based on their previous projects and experience,know that they play a major role in collaborating with their assemblycolleagues to minimize or eliminate these problems.

They knowdefects can result from machine limitations, incorrectly designed-intolerances, and board spacings. Design-for-assembly (DFA) takes intoconsideration physical properties, height, length, and package-relatedlimitations. If an embedded design is densely populated with 0201 or01005-type packages and tight assembly processes aren’t specified, thiscombination can create multiple board defects, such as tombstoning,skewing of components, and inactivation of flux with solder paste.

Anembedded designer also has to know the limitations of variousfabrication and assembly process machines. Those include pick-and-place,AOI, re-flow, wave solder, and test systems, among others. The boardshould be designed keeping in mind mechanical and other tolerances suchas the size of the board, and in case of smaller boards, size of thepanel, as each machine has physical size limitations. Also, there aresome height-related restrictions, especially in the case of a flyingprobe tester, whereby using taller components might hinder and restrictmovement of the flying probes.

Components can be designed andspaced too close to each other or to the edge of the board. Consequently, this error or oversight poses limitations for thepick-and-place machine when placement is performed. Hand placement thenhas to be used, creating reliability issues and likely leading todefects. An alternative is to re-design the board, which involves acostly and time-consuming re-fabrication.

A component placement– such as a 0.4 mil pitch BGA, for example — requires considerablytighter placement tolerance than a 0.7 or 0.8 mil pitch BGA, and thus itdemands more placement precision performed by expensive pick-and-placeequipment. Even then, at 0.4-mil pitch, reliability and repeatabilitycan continue to be issues unless proper design measures are taken.

Training is critical
Two key questions the embedded designer and his or her OEM organization has to ask are:

  • “What kind of training and experience do my assembly and manufacturing people have to ensure my design can be manufactured?”
  • “What can I do as an embedded designer collaborating with assembly and manufacturing engineering to assure my design is ideal for manufacture?”

An OEM or supporting electronics manufacturing services(EMS) provider must have assurances assembly and manufacturingoperations are well-organized, trained, and IPC certified. The bestscenario is to have ample redundancy so that there are multipleengineers and technicians on the floor who are capable of accuratelyoperating assembly and manufacturing systems. Re-training floorpersonnel to the latest processes and techniques should be ongoing andis especially critical when an operating system in a piece of equipmentis changed or upgraded.

Also, assembly and manufacturing staffs need to be periodically re-certified to the latest Association Connecting Electronics Industries (IPC) standards, ISO (International Standards Organization) procedures,and the latest manufacturing practices. This keeps staffs up-to-datewith on-going changes and their skills sharp.

Stencil quality and SPI
Stencildesign and all associated aspects are crucial to ensure solder paste isprecisely deposited on surface mount technology (SMT) pads of aboard. A stencil dispenses the paste on the SMT pads. Its thickness, theaperture sizes, and frame or non-frame stencils are factorscontributing to paste dispensing and solder quality on the PCB. This is acritical step prior to applying a thermal profile to reflow solderingafter the components are placed on the board.

Stencil thicknessranges from 2 to 7 mils and determines the amount of paste to bedispensed on the SMT pads. Large SMT component packages like the 1206-,0805-, and 0603-type passive devices need an 5 to 7 mil thick stencilsince it deposits a larger amount of paste on these components.

Smallerpackages such as the 0403- and 0201-type passive devices must go with athinner — about 3 to 5 mil — stencil. This means using a smalleramount of solder paste on the board since pad size issmall. Considerably thinner 3 to 5 mil stencils are used for the tiniest0201- and 01005-type packages for passive devices with the amount ofpaste deposited about a small drop.

Using the wrong stencilthickness creates performance problems. For instance, a 7-mil thickstencil dispensing paste on 0102-type components deposits too muchpaste. During reflow, it will short all capacitors, resistors, andinductors due to excessive paste. On the other hand, using a thinner3-mil stencil on larger 1206- or 0805-type packages results in coldsolders or voids during reflow because of insufficient amount of solderpaste being applied on the pads of the components.

Aside from thecritical collaboration between embedded designer and assemblyengineering and high-caliber, up-to-date training, it’s also importantfor embedded designers to get an understanding of today’s laser SolderPaste-height Inspection (SPI). This is the third major part ofminimizing defects and involves using effective SPI systems operated byhighly trained technicians.

In short, SPI uses laser technologyto detect the amount of solder paste deposited on the surface mount(SMT) pads of a BGA or other device. It shoots an extremely thin sliceof laser light through its lens and into the solder paste to measure thedepth of paste deposited on the SMT pads. The laser light inspects thesolder paste first before reaching the PCB’s surface and then calculatespaste amount from the PCB’s surface to the highest level.

Today,all the buzz in PCB manufacturing circles is about 5 and 3 dimension(5D and 3D) solder paste height inspection. However, most EMS providersand contract manufacturers (CMs) aren’t quite ready to fork over thecapital expense (CAPEX) for these highly advanced inspection systems.

Insome cases, 3D SPI is being used. However, most of the industrycontinues to use 2D SPI and places increasing emphasis on up-to-datepersonnel training. 5D SPI combines the 2D aspects of image analysiswith the 3D volumetric measurements to represent state-of-the-art inthese types of systems.

Two types of 3D SPI are true 3Dmeasurement and 3D rendering of a 2D dimension, whereby 2D images, usingsome algorithms, create 3D images for better recognition andmeasurement. The former is acceptable, but isn’t as accurate or aseffective as far as measurement and tolerance factors compared to true3D measurement SPI. Also, an important aspect of a good SPI system isfield of view (FOV). When the FOV is larger, the image of the solderpaste is bigger for a considerably more accurate viewing. Here, the SPIsystem shoots in a ray of light rather than a single beam.

With2D SPI taking on the majority of solder paste inspection duties, itbecomes increasingly more important to maintain well-trained andcertified assembly personnel with a good eye and who are exceptionallyvigilant at seeking out defects.

Zulki Khan is the Founder and President of NexLogic Technologies, Inc . ,San Jose, CA, an ISO 9001:2008 Certified Company, ISO 13485 certifiedfor medical electronics, and a RoHS compliant EMS provider. Prior toNexLogic, he was General Manager for Imagineering, Inc., Schaumburg,IL. He has also worked on high-speed PCB designs with signal integrityanalysis. He holds a B.S.E.E. from N.E.D University and an M.B.A fromUniversity of Iowa and is a frequent author of contributed articles toEMS industry publications.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.