Avoiding latchup in CMOS chips - Embedded.com

Avoiding latchup in CMOS chips

If you leave signals applied to the inputs of a CMOS chip with the power turned off, the chip might explode when you re-apply power. This is called latchup. Similarly, if you drag the outputs of a CMOS chip above or below the power supply rails you can latchup the part. Latchup is not always destructive. Sometimes the part heats up, but when you remove all power and signals, the chip has survived the latchup condition. It does not matter if the CMOS IC is a microcontroller, an operational amplifier, an analog-to-digital converter (ADC), logic, or analog multiplexor.

Latchup becomes a real problem when you try to power up and down different sections of your design to save power. It is also a problem when you have cables or inputs from other devices going directly to your chip. Another common problem is when a CMOS output is connected to a large capacitive load. The part will go into latchup the moment you turn off its power. As long as you don’t turn the power back on for a few moments you are fine, the energy in the capacitor dissipates and the CMOS part is out of latchup. But if someone cycles power quickly, or if there is a momentary dropout or glitch, boom, the part blows its lid.

I got to thinking about latchup when I heard that the Atmel SAM L21 microcontroller has five separate power domains inside the chip. Rather than just kill the clock to unneeded circuit blocks, the SAM L21 turns off power to the block. This is great, since it removes any leakage current contributed by that block. The IC designers can use tiny fast cheap transistors that tend to have higher leakage, but it does not matter. When you turn off the circuit block, with zero volts across the logic gates there can be no leakage.

The IC designers who did the SAM L21 had to suffer with all the same latchup problems as we systems folks do. One of the tricks I have used is to put high-value resistors in series with the inputs to the device you need to turn on and off (Figure 1a ). Another is to use Schottky diode clamps on the inputs and outputs, so they can never get more than a diode drop (0.6V) above or below the rails (Figure 1b ).

Figure 1 To prevent latchup in CMOS chips you can put high-value resistors between the inputs and outputs (a). Another solution is to put Schottky diode clamps in the wires to prevent them from going more than 0.3V above or below the switched Vcc net (b). Note that power will still flow into the switched chip via the input pins and internal ESD diodes.

It’s nice to have discrete diode clamps on your schematic to remind you that you already have them inside the chip in the form of ESD (electrostatic discharge) diodes. I have seen engineers struggle for hours trying to figure out why an expensive military electronics box was not working quite right. It was kind of working, but nothing made sense. The problem was they had not turned on power to the box. The CMOS circuitry was being powered by the inputs from another box or the test equipment (Figure 2 ).

Figure 2 Voltage on the input pin of most any IC will flow through its ESD diode structure and self-power the chip and worse yet, any chips that are connected to the same power net.

Don’t laugh, it has happened to a lot of good engineers, and you might be next. Since CMOS circuitry needs so little power, the inputs can flip the internal ESD diodes around and you will not only power the chip’s Vcc line, that Vcc line connects to all the other chips and they will be powered up too. So then you risk latching up the first IC and you are not really saving power in the first place.

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