Back to the basics: Achieving optimum ADC performance in your embedded systems design - Embedded.com

Back to the basics: Achieving optimum ADC performance in your embedded systems design

ADCs convert real-world analog signals such as sound, temperature,pressure and light into digital signals that can be processed in thedigital domain.

Analog design engineers like to say “The world is analog,” but mostsignal processing is done by digital computers today – the days ofanalog computers are long over. This article gives an overview of ADCsand recommendations on how to apply them successfully.

ADCs (Figure 1 below ) arefound in so many applications that they are almost a commodity.Historically, converters were components requiring specializedknowledge to design and manufacture, resulting in expensive solutions,such as a 12bit/500kHz ADC sold for about $270 in 1975.

Figure1. ADCs are used in communication, instrumentation and measurement, andcomputer systems, where they can facilitate DSP, information storage orboth.

Modern converters have come down in price over the years,capitalizing on the same technology advances as digital ICs. That same12bit/500kHz function is available today for less than $1.

ADCs are commonly used in communication, instrumentation andmeasurement, and computer systems, where they can facilitate DSP,information storage or both.

The ADC function is often integrated along with digital circuitry onthe same chip, but there are also applications where performancerequirements dictate that a standalone ADC must be used. The cellphoneis an example where the ADC function has been integrated into thedigital chip, while the cellular base station (with its higherrequirements) relies on separate standalone ADCs, which can deliver theultimate in performance.

ADCs contain the following:

Analog input ( s ) – Single and multiple channels are available.

Reference input – This voltage can be supplied externally or maybe inside the ADC.

Clock input -It is typically external and determines theconversion rate of the ADC.

Power supply input(s) – Often, there are both analog and digitalsupply pins.

Digital output – ADCs can have parallel or serial digital outputs.

While ADCs may appear to be simple, they must be applied correctlyto achieve optimum performance. ADCs exhibit some of the sameperformance limitations as simple analog amplifiers – finite gain,offset voltages, common mode input-voltage limitations and harmonicdistortion are a few of them.

The sampling nature of the ADC introduces the additionalconsiderations of clock jitter and aliasing. These general guidelineswill help realize the full performance of the ADC in your design.

Keep it clean
Careful attention must be paid to keeping the analog signal to the ADCas clean as possible. “Garbage in” typically results in “digitizedgarbage out.” The analog signal path should be kept clear of anyfast-switching digital-signal lines that may couple into the analogpath.

While the figure shows a single- ended analog input, differentialanalog inputs have become more common in high-performance ADCs. Drivingan ADC differentially provides greater common-mode noise rejection andtypically allows for better AC performance due to smaller on-chipsignal swings.

Differential drive is typically accomplished using a differentialamplifier or transformer. A transformer usually provides betterperformance than an amplifier because the active amplifier is anadditional noise source, which affects overall performance.

However, transformers are not a viable solution when you need toprocess signals with DC information because of their inherentDC-blocking characteristics.

The driving amplifier's noise and linearity performance must beconsidered when designing the pre-drive circuitry. Note that sincehigh-performance ADCs often have very high input bandwidth, filteringdirectly at the ADC's input pins reduces the amount of wideband noisebeing aliased down to the baseband. The reference input should betreated as another analog input and kept clean as possible.

Any noise on the reference voltage (V ref ) is indistinguishable fromnoise on the analog signal. Typically, the ADC datasheet specifies therequired decoupling capacitors. These caps should be placed as close tothe ADC as possible.

PCB designers sometimes place decoupling capacitors on the backsideof the PCB to conserve board space. This should be avoided if possible,since the inductance of the vias reduces the capacitor's effectivenessat high frequencies.

Vref  usually sets the full-scale range of the ADC,so reducing the value of the Vref   voltage reduces theleast significant bit (LSB) value of the ADC, making the ADC moresensitive to noise in the system. A 1V full-scale 10bit ADC has an LSBvalue equal to 1V/210 = ~ 1mV.

Noise sources
Depending on the application, the digital clock input may be just ascritical as the analog inputs. There are two major sources of noise inthe ADC: one due to the quantization of the input signal (proportionalto the number of bits in the ADC) and the other due to clock jitter(sampling the input at the wrong time).

Quantization noise limits the maximum possible SNR in anon-oversampled ADC application according to the formula:

SNR = 6.02N + 1.76dB,

where N is the number of bits. Intuitively, this makes sense -every time you add a bit, you double the total number of ADC codes andcut the quantization uncertainty in half (6dB).

Thus, a 10bit ADC is theoretically capable of providing 61.96dB SNR.Any jitter on the sampling clock reduces this further according to theequation:

where SNR j is the jitter-limited SNR, f a is the analog input frequency, and t j is the rms clock jitter.

A sampling clock with jitter equal to 8 picoseconds (ps) digitizinga 70MHz analogsignal results in a jitter-limited SNR of approximately 49dB,effectively reducing the effectiveness of a 10 bit ADC to about 8bits.The clock jitter must be < 2ps to achieve an SNR equivalent to10 bits.

There are many other second-order contributors to SNR, but the givenequations are a good first-order approximation. Differential clockingis often used to reduce jitter. Most ADCs have separate power-supplyinputs: one for the analog circuitry and another for the digital.

Adequate decoupling capacitors, which are located as close to theADC as possible, are recommended. Minimize the use of PCB vias and thetrace length from the ADC power pin to the decoupling capacitor.

This is to keep inductance between the ADC and the capacitor to aminimum. As with reference voltage decoupling, board designerssometimes place decoupling capacitors on the back side of the PCB undera chip to conserve board space. This should be avoided for the samereasons.

The ADC's datasheet usually shows the recommended decoupling scheme.Dedicated PCB planes for both supply and ground voltages are oftennecessary to achieve the specified performance.

An ADC's switching digital outputs can generate noise transientsthat can couple back to the sensitive analog portion of the ADC,causing errors.

Reducing the capacitive load that the ADC drives by minimizing theoutput trace lengths can help here. Placing series resistors right atthe ADC outputs to reduce the output current spikes is also helpful.Moreover, the ADC's datasheet usually has a recommendation.

Gary Hendrickson is StaffApplications Engineer in the Analog & Mixed Signal Products Groupat Intersil Corp.

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