Balancing flexibility versus cost in discrete USB transceiver designs -

Balancing flexibility versus cost in discrete USB transceiver designs


The integration of USB transceivers intoASICs or power-management ICs(PMICs) has been an industry trend in recent years, resulting in alimited opportunity for discrete PHY transceivers.

With surging demand for high-technology consumer products, OEMs andreference-design houses must balance the high cost of chipsets andinnovation with consumers' clamor for low-cost products. Severaldiscrete transceivers are available, but the need to differentiate hasled to product variations and, consequently, a lot of confusion.

In some cases, an exact replacement device may not be available andelectrical characteristics may have to be traded off. While cost is animportant factor, performance should not be compromised.

Today, selection of discrete transceivers often depends on ESD capability, integrated pull-up resistors and I/O host configuration(differential or single-ended). With many applications sharing D+/D-cable signal lines, there is a need to understand discrete- transceiverfunctionality in both disable and sharing modes.

Transceivers must be compatible with baseband or applicationprocessor I/O configurations. In 1997, the discrete USB1.1 transceivershad no integrated regulator or additional low-voltage host supply . Thedesign was a discrete way of providing a single supply to thetransceiver. .As it gained popularity, the 2.7V type was recognized foroffering multiple supplies, allowing the integrated regulatortransceiver to penetrate the market.

Figure 1 below illustratesthe architecture of the two devices. The USB1T1103 uses I/O pinsinterfacing with the host versus the traditional USB1.1 transceiver.For the USB1T11A type architecture, a designer must ensure that thereis a way to turn off the supply to 1.5k to meet the USB 2.0specification.

This is often overlooked when a product is subjected to USB-IF1compliance testing.Initial considerations when selecting a USBtransceiver include whether I/O or separate host inputs and outputs arepreferred; FS or FS/LS driver capability; single-ended or differentialhost interface; and separate VCC io and Vbus monitoring capability.

Figure1. Features touted by IC vendors include ESD to ± 15kV,enumeration pin and integrated 1.5k-ohm pull-up.

Typically the choice for I/O configuration is determined by theapplication or baseband processor used by the reference design. Otherfeatures touted by IC vendors are ESD to ± 15kV, enumeration pin(configuration in Figure 1 above )and integrated 1.5 kohm pull-up.

In ultraportable designs, battery life is critical – thus, it isimportant to fully understand potential current consumption duringsuspend, disable and sharing modes.

Disable mode puts the interface between the transceiver and thebaseband or processor in high impedance. Sharing mode, on the otherhand, can disconnect the Vbus/Vreg supplies such that the D+/D- signallines are shared by another function within the product. The USBtransceiver driver enters a high-impedance state in this mode.

Table 1 below highlightssome of the key differences between discrete transceivers available,which may be common across IC vendors.In addition to the interfacecharacteristics, there are subtle differences in transceivers'integrated 1.5 kilo-ohm pull-up resistors, enumeration pin (undersoftware control ) that disconnect the 3.3V supply from the pull-up,latched RCV data during SEO event and series resistor for USB data linedriver impedance.

Table1. Some key differences between discrete transceivers available may becommon across IC vendors.

ESD components
Every IC vendor specifies a series resistor different from those usedby its competitors since it is a function of its process technology andoutput buffer design structure. This practice may pose problems,particularly when manufacturers seek a second source device or chooseto replace a current vendor.

In a well-designed application, conforming to USB 2.0 specificationsand design guidelines may have less impact than what the manufacturerperceives. If a slight increase in edge rates is acceptable, the lowerresistor is used as the manufacturing insert.

Typically, the lower the Rs on the datasheet, the higher the silicondriver impedance becomes, which in turn shows the potential for asmaller NMOS pulldown (lowercapacitance) and slightly lower drivesource/sink capability of transceiver output structures.

Having chosen the Rs resistor for the transceiver output, externalESD or choke filter components are added on the D+/D- pins. There ismuch confusion about which ESD rating to target. Many engineers willsimply respond to the value of ESD on the datasheet (8kV vs. 15kV)without understanding exactly how that ESD specification wascharacterized.

In some cases, extra capacitance (typically 4.7 microFarad) isadded, cutting the edge of the ESD test pulse. It is thus important tocheck the test schematic on the specific IC manufacturer datasheet.

The USB1T1103, for example, is 15kV (HBM Mil 883E -contact) for D+/D- with no extra capacitance. If the designer specifies the useof additional EMI and ESD components, the series resistance of thecommon mode chokes must be taken into account.

This resistance, often 4-8 ohm, has to be accounted for and Rs mayneed to be modified to meet the USB2.0 driver impedance specifications.In the case of the ESD external components, it is also important tounderstand the capacitance characteristics to ensure that USB2.0requirements are met and that the ESD immunity is modified by thiscapacitance.

Edge rates
Another aspect of USB design that is often misinterpreted duringproduct design is the USB legacy edge rates and their matchingtolerance. These are specified into a lumped load, not a distributedload, hub or gold tree.

Some customers have created their own internal QA environmentguidelines, requiring correlation between edge rate, edge-rate matchingand EMIcompliance based onproven design practices for shielding andspecific test environments. These guidelines obviously do not guaranteeUSB-IF compliance.

Hence, when a product is due for release and commercial compliancesoftware indicates non-conformity to the specification (e.g. 20ns forFS), it is important to understand the differences between thespecification and the system environment when interpreting results.Absolute measurement values for rise and fall times are only valuablefor reference and comparison, since it is the eye mask that iscritical.

Figure2. By increasing Rs, it can easily be proven that the eye is notviolated with Edge rates as high as 25ns.

Failing the eye in the current USB-IF compliance testing for FS/LSapplications spells more problems for the product. It typicallyindicates poor hub design, mismatched PCB characteristics for D+/D-signal lines or excessive capacitance/resistance to the USB2.0specification.

For example, when tested in a hub containing uncertified Gold Treedevices, it is highly possible to measure 19-25ns rise times. But whenvalidated in a characterization test fixture (lumped 50 pF load),measurements of 8-11ns may be common.

Upon seeing 19-25 ns measurements, one is led to believe that thesilicon is defective; but with problem solving, one can lay the blameon excessive hub (or peripheral) capacitance, poor PCB design, a noisefilter external device with very high series resistance/capacitance orincorrect series resistor.

The current USB-IF compliance testing reports on the eye diagram,with rise/fall times considered as informational. By increasing Rs, itcan easily be proved that the eye is not violated with edge rates ashigh as 25ns.

Failure to meet these Edge-rate criteria does not necessarily meanthat a product will not function in a USB system. Conformity with thesecriteria, however, boosts consumer confidence in a product andguarantees USB-IF compliance from a certified test lab.

Figures 2 above and Figure 3 , below depict the eyediagram and packet waveform for a prototype product using a discretetransceiver (FSC USB1T1103) with a 30 ohm series resistor, measured atTier 6 using the TektronixTDSUSB2 software and test jig.

Figure3. Packet diagram for FSC USB1T1103 with Rs=30 ohms, 1m cable, Tier 6.

In choosing the best discrete USB transceiver, it is important tounderstand the following:

1) subtlefeatures of the individual transceiver relative to powersupply configurations;

2) output stateswhen in sharing mode;

3) defaultapplication processor output states (pulled high, pulledlow, programmable, external resistors);

4) seriesresistor recommended by the silicon vendor; and,

5) external ESDor EMI filter component impact on the applicationenvironment.

By recognizing the origins and definitions of legacy specificationsand observing the recommended “good USB design guidelines”, developerscan design USB-IF compliant products using discrete transceivers fromdifferent silicon vendors on their approved vendor list.

To get optimal performance, the designer must fully understand thevarious aspects of the USB 2.0 environment and its interaction withnon-USB related components, and the relative trade-offs forconsideration. In the case of ESD immunity, the designer must know theexact test setup and how the device was characterized.

Graham Connolly isApplication/Definition Engineer at Fairchild Semiconductor.

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