Balancing memory performance and power consumption in IoT applications -

Balancing memory performance and power consumption in IoT applications


Two critical criteria for the selection of electronic components for IoT applications are power budget and performance. Ever since the beginning of electronics, there has been a tradeoff between these two – either you get the best power consumption or you get the highest performance. System architects have different requirements for different components in the system, based on the application. For example, a system may require a high performance controller but a low power memory. A typical case is a wearable device, where the controller needs to be powerful but as the SRAM is used as a scratchpad, it is expected to have the lowest possible power consumption.

Most systems fall into the following broad categories:

  1. Always On: These systems don’t have power consumption as a major criterion since they’re almost always powered by an uninterrupted power source. Such systems need the highest performance components possible, BOM budget permitting. Most devices that are plugged into a wall socket fall under this category.

  2. Battery Powered: These systems are at the other end of the power-performance spectrum. They are powered entirely by an on-board battery. Such systems tend to value power consumption above all else. Such systems also typically prioritize small form factor since they are usually portable. Examples systems include handheld devices we use daily.

  3. Battery-Backed Systems: These systems lie somewhere between an always on system and a battery powered system. They access external power sources but can lose access to their power supply. To avoid losing critical data during these power failures, system designers provide a small battery (typically a 240mAh coin cell) to backup critical functions like SRAM and the real-time clock (RTC). These systems usually prioritize high performance, but require that certain components be low power so that they can function solely on backup power.

There has been a technological reason for this tradeoff between performance and power consumption in SRAMs. Low-power SRAMs employ special GIDL (Gate-induced Drain Leakage) control techniques to control stand-by current and thus standby power consumption. Extra transistors are added in the pull-up or pull-down path, resulting in access delay increases and hence longer access times. With fast SRAMs, access time is the highest priority and such techniques cannot be used. Moreover, the transistors are scaled up in size to increase charge flow. This scaling-up reduces propagation delay but increases power consumption.

However, a wide range of applications are migrating wired always-on devices to battery-backed or battery powered mobile versions. This new generation of devices — medical, handheld, consumer, communication, industrial –  are all driven by the IoT. They are revolutionizing the way devices function and communicate. For such devices, neither the components designed for high performance nor those for low power can meet design requirements. High performance components have high current consumption and thus drain the battery too quickly. Low-power components are not fast enough to handle the demands of these complex devices. There is a need for devices that are both high performance and low power. This is especially critical for memory since a system is truly only as fast as its slowest component, which in many cases is the external memory.

The need for lower power has affected microcontrollers first, forcing manufacturers to find alternatives to the traditional two operating modes – active and standby. This led companies like TI and NXP to introduce MCUs with a special low-power mode of operation called deep power down or deep sleep. These controllers run at full speed during normal operation but can drop into low-power modes when this performance is not required. These low power modes reduce power consumption without compromising high performance. Today’s controllers are capable of running at speeds above 100 MHz, significantly faster than previous generations of cutting-edge controllers. However just optimizing the controller in IoT devices isn’t sufficient to meet their stringent power budgets. During low-power mode, peripherals and memory devices are also expected to save power. The onus of power management has now shifted to memory devices interfaced to such systems.

Many portable systems execute code from Flash but use SRAMs as a cache to store results and initialization variables. Compared to other storage memories like DRAM and Flash, SRAM is limited in terms of density: the highest density SRAM available today is 8 MB, while DRAMs are available in multiples of GBs. However, it is difficult for an MCU to interface directly with a DRAM or Flash as these memories typically have long write cycles and are unable to keep pace with the MCU. Moreover, DRAMs have high power consumption due to their refresh cycles. An MCU that operates at high speed needs a cache that can store critical data and execute calculations quickly without a significant power penalty. SRAM is the best fit to act as a cache between the MCU and the storage memory.

SRAMs alternate between active and standby states, with the data expected to be non-volatile when the power goes off. These SRAMs are battery-backed, usually by a single coin battery. Such systems pose unusual challenges for the SRAM. As long as the system is active, they require the highest performance SRAM they can get, since it serves as a high-speed cache in these applications. However, they also need low power consumption in case the system has to switch to battery power.

On power failure, the SRAM is switched to the on-board battery and is disabled by the supervisor chip. The system can remain in this mode for as long as the battery lasts. Once the board power supply resumes, the supervisor chip will gradually power the SRAM with the board supply. Typically, these chips take between 1 and 10 ms for the transition. This time doesn’t hinder the system as the controller also requires time to come out of it power-on-reset routine. Refer to Design Recommendations for Battery Backed SRAMs to learn more specific implementation details.

Considering the above factors, SRAMs have tried over the years to balance the trade-off between fast and low power products. One of those solutions is a hybrid device that falls midway between fast and low-power in both access time and power consumption. However, these hybrid SRAMs are unable to meet the performance requirements expected from Fast SRAMs. The best approach is a Fast SRAM with on-chip power management, ensuring both high-performance and low-power.

SRAMs with on-chip power management work in a similar way as MCUs with on-chip power management. In addition to active and standby modes of operation, there is a deep sleep mode of operation. Such a setup allows the SRAM to access data at full speed during its standard mode of operation. During the deep sleep mode of operation, the device doesn’t perform any functions and so can keep current consumption extremely low, on the order of 1000 times less than the standard standby consumption of Fast SRAMs.Table 1 shows a comparison of power and access time for the two common types of SRAMs – Fast and low power – as well as Fast SRAM with Deep-Sleep.

Table 1: Comparison of different types of SRAM (Source: Cypress)

The numbers clearly demonstrate the advantage of using a “Fast with Deep Sleep” SRAM over a standard Fast SRAM. This advantage will be more prominent in applications where the SRAM is in standby mode most the time.

In many latest generation battery-powered systems, getting to the sweet spot for memory power consumption is a fine balance of time needed to store the data and power consumption during the process. For example, consider an application that needs to write 100 Kb of data every 1 millisecond. If we are to use a Fast SRAM, it takes 10ns to write 2 bytes of data. Thus, a Fast SRAM will have a 6% duty cycle, which translates to 130 Watt-Hour (WH) over 1000 hours of operation. By contrast, a low power SRAM required to do the same task will have a 31% duty cycle, consuming much less power at 2WH. However, the SRAM isn’t the only component that’s awake while the SRAM is being written to. When factoring the MCU’s power consumption in, the ratio could skew in favor of Fast SRAMs.

A Fast SRAM with Deep Sleep completely eliminates the need to evaluate this trade off. With the duty cycle of a Fast SRAM and the standby current of a Low-Power SRAM, these SRAM consume significantly lower power than Fast SRAM with a much shorter duty cycle than low power SRAMs. This means the MCU is required to stay active for a shorter time while writing data to the SRAM. For battery-powered systems, the overall drop in system power due to the lower duty cycle of Fast SRAM with Deep-Sleep can be quite significant. Table 2 shows the results of battery-powered tests we conducted at Cypress. The shorter duty cycle is due to Deep Sleep extending battery life by around 20% compared to systems that use a low power SRAM instead.

Table 2. A comparison of SRAM power consumption (in WH) by the three types of SRAM for a sampling of duty cycles. (Source: Cypress)

There is an important factor to consider when using deep-sleep mode (be it MCU or SRAM) – time taken to enter and exit deep-sleep mode. If the time interval between two active periods is too short in comparison to the time taken by the SRAM to enter or come out of deep-sleep mode, then the method will not be useful. This could potentially be the biggest hurdle to the widespread adoption of SRAMs with deep-sleep mode. In the case of Cypress’ Fast SRAMs with Deep-Sleep, this figure is 300µs (max).

A common concern, especially in battery-backed systems, is that a new feature like deep sleep will require extensive redesign. This is not the case when transitioning a standard battery-backed system that uses a supervisor chip. In a standard battery-backed system, the address lines, data lines, and control signals are driven by the processor. However, the active low chip enable of the SRAM is driven by the supervisor chip, which adds no significant overhead during normal operations. During power failure, the supervisor chip seamlessly switches from the board power supply to the battery supply and disables the SRAM, thereby preventing data loss.

This same system can be easily migrated to Fast SRAM with Deep-Sleep capability. To use the deep sleep functionality, there is a special pin (DS), which is toggled active low to enter deep-sleep mode. The equivalent pin on a standard Fast SRAM happens to be NC (no-connect). Thus, upgrading from a standard Fast SRAM to a Fast SRAM with deep sleep requires minimal design effort (one extra pin has to be interfaced).

During normal operation, the SRAM can be operated at fast speeds. During a power failure, the SRAM can be automatically switched to deep sleep mode by asserting the deep sleep signal. When the power fails, the supervisor chip disables the SRAM and pulls down the deep sleep pin, which will automatically switches the SRAM into deep sleep mode. Once the processor has booted, the deep sleep pin is switched high to restore the SRAM into a standard high speed SRAM. The application note Power Saving SRAMs outlines the implementation of such a switch and explains the critical timing considerations that need to be managed by the supervisor chip during power failure events.

Reuben George works in Product Marketing for the Memory Products Division at Cypress Semiconductor. He holds a BE in Electrical & Electronics Engineering from the prestigious Birla Institute of Technology and Science (BITS), Pilani in Rajasthan, India.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.