The integration of analog with digital and the increase number of on-chip features in mixed-signal controllers demand more complex I/O structures. Though they are sometimes some of the most neglected features of a chip, I/O (Input / Output pins) can represent a great deal of functionality in a SoC (System on Chip).
The I/O structure in today’s SoC is so feature-rich that a full understanding of their capabilities is important to understanding how to do more effective system design, and achieving greater value from the SoC.
In this two part article, we will discuss the following:
* basic understanding of the structure of an I/O block in any digital device
* different specifications of pin, which need to be understood, while selecting the device for application
* different variants of configurations of I/O block which need to be used for different application requirements
* choosing the particular configuration that will achieve both reduced BOM cost and improved system performance
Drive mode is the way the pin is driven based on its output/input state. In this section we will look at some of the drive modes generally used in a generic System on Chip. When it comes to drive modes, it is mainly about digital, as high impedance is the only drive mode used for analog apart from some exceptions. These drive modes can be named differently by different SoC manufacturers but can be recognized easily by looking at their I/O architecture. If these drive modes are used appropriately, it will help to yield better system integration and reduce BOM cost. Let us look at the very basic output stage of an I/O cell.
Basic digital output cell: As shown below in Figure 1 below , the output driver available in most of the controllers. This drive mode may be known as strong or CMOS drive mode in different controllers.
If we look at it closely, it is nothing but the inverter which has its input controlled by a register bit generally called the data register in. (The reason it is called strong is that the CMOS inverter drives both ‘1’ and ‘0’ at strong levels).
Figure 1: CMOS drive mode (CMOS inverter)
All other drive modes are nothing but slight variation of this CMOS inverter to achieve different system topologies. Let us look into these variations.
Resistive Pull up/Down: This drive mode helps to reduce BOM in most of the applications so we are discussing it at first. In resistive pull up/ pull down mode, a resistance is introduced between the drain of MOS transistors and pin pad (Figure 2 below ).
Figure 2: Resistive Pull up/ Pull down drive mode
So, it limits the current flowing through the pin and serves the same purpose as any other external pull up/ pull down resistance does. In applications, where a switch needs to be interfaced, a pull up / pull down resistance is needed to keep the input at a defined logic.
This pulling up/down of the pin can provide a stable default state and thus avoid random fluctuation that could occur due to noise. Now, the resistance internal to GPIO cell can be used for this purpose in a resistive pull up/ down mode. (Figure 3 below ).
Figure 3: Use of internal pull up resistance to interface switch
Also, there are cases in communication protocols where the pins act as bidirectional interfaces. In such an instance we tend to use external pull up/ pull down resistors.
One point worth to be noted is, generally these internal resistances are very inaccurate. So, they cannot be used in case precision is one of requirement.
Open drain modes: The open drain mode is the case where one output state of the pin activates its corresponding transistor but the complimentary state is a high Z. For example in case of open drain drives low drive mode, the pin is driven strong low when data register bit for the pin is ‘0’ and it is high Z when the data register bit is ‘1’.
This mode is useful when used in communication protocols like I2C where the pins have a bidirectional nature. This would be achieved by having an open drain mode with an external pull up resistor. Thus in the high state of the pin it is waiting for activity from the other side of the line. Figure 4 below shows the drive structure for the Open drain modes.
Figure 4: Open drain drive modes
Usage mentioned above is the standard use case for open drain drive mode. But there are so many other functionalities that can be implemented using this drive mode.
For example, recently we used this drive mode to replace one analog switch. Yes an analog switch! In this application, a capacitor needed to be charged with an IDAC and then after a fixed amount of time, discharged to ground.
The IDAC connects to the capacitor through a pin on the device which is configured for an open drain drive low with a value of one written to its data register. This meant that the pin was treated as a high impedance, which is ideal for analog signals.
The discharge required the capacitor to be connected to ground. This was achieved by writing a zero into the data register of the pin. Simultaneously, disabling the IDAC avoided current flowing into the pin grounds.
Another advantage of using this implementation is lesser discharge path resistance as no analog switches are involved apart from one NMOS transistor.
High impedance mode: This mode is generally used as an input drive mode for the pin. In this mode the output drive circuitry of the pin is disabled. Many controllers like the Cypress PSoC3/5 use this mode in a digital and analog perspective.In a digital perspective the pin drives an input threshold Schmitt trigger to drive some internal digital circuitry. After this, the signal (Digital now) changes the state of a pin state register. In some of the devices like PSoC3/5 which have a programmable digital structure implemented inside the device, the same digital signal is then routed into the digital routing structure.
When the pin is used to bring as an analog interface it is still maintained in a High impedance state since you don’t want any kind of output drives on it. But an internal routing architecture might take care of getting the analog signals to their destinations.
This is normally achieved by the use of internal analog switches in the device which can switch internal analog signals onto the pin. Devices like the PSoC3/5 have a versatile analog architecture implementing multiple analog components like ADCs and Opamps internal to the device. The signals into or out of such blocks require to come to pins with high impedance drive mode.
Drive strength & driving higher current loads
Another major factor a designer should consider while designing a circuit is the case where his outputs are driving loads. Many a time a digital output might be used to drive a component like an LED or even drive other loads that actuate another mechanism.
In these cases it is very important to understand the drive strength of the pin driving the output circuitry. For example if the pins were driving LEDs that take up a load current of 20mA, then the pins should be able to support this load requirement.
In cases where a single pin cannot support this huge current requirement; the user can gang multiple pins together to provide a cumulative current capability.
So, it is not always needed to use external drives to support current more than the specified current for a single GPIO as long as enough pins are available to give cumulative current as per requirements.
In some devices the maximum sink current for the pin would be higher than the max source current. In such circumstances the user can make efficient design for the LED circuitry to sink current than to source it. Thus the advantage of having a higher sink current is utilized by the design.
Slew rate and its effects
Slew rate is one of the most important parameter to be looked at. Slew rate defines the rise time and fall time of the digital output. High slew rate results in fast rise and fall times and on the other hand slow slew rate does the opposite.
In GPIOs, slew rate is reduced by changing the RC time constant of the input of CMOS inverter (a series resistance is inserted between the invertors used for inversion and actual output driver).
The drive circuit shown in Figure 1 possesses the high slew rate while the one shown in Figure 5 below possesses the slow slew rate.
Now the question is, which one to use when?. To determine this, let us look into the advantages and disadvantages of each.
Fast slew rate: Due to fast rise time and fall time, output contains high frequency components. It leads to two major issues. First is electromagnetic interference (EMI) and second is interference with other signals on the board. High frequency components get radiated even with small trace length (required antenna length is proportional to wavelength of signal).
So, if a high slew rate is used, it may create EMI issues in the design. High slew rate signals tend to get coupled on adjacent traces and create issues especially with analog signals.
There is a parasitic capacitance between traces. As shown in Equation 1, below , if we look at the impedance of capacitor, it is inversely proportional to the frequency.
In this equation, f is the frequency and C is value of capacitor. So, at high frequency coupling is increased between traces due to a low impedance path.
Slow slew rate: Generally, to increase the rise time and fall time, input to the CMOS inverter is slowed down using the series resistance as shown in Figure 5 below.
Figure 5: Slow slew rate
Opposed to high slew rate, slow slew rate is least prone to EMI and inter-trace coupling. The only disadvantage of slow slew rate is higher power consumption. The NMOS transistor will operate in saturation as per Equation 2 below.
The PMOS transistor will operate in saturation as per Equation 3 below.
Where VDS is drain to source voltage, VGS is gate to source voltage and VT0 is threshold voltage of the transistor. Figure 6 below shows the VTC (Voltage Transfer Curve) characteristics of CMOS inverter.
Figure 6: Voltage transfer curve of CMOS inverter
As can be seen from Figure 6 above, when Vin is about Vdd/2 both NMOS and PMOS are in saturation. When both transistors are in saturation, very high current flows between supply rail and ground through these transistors.
(Note: This figure is just an example. The transfer curve can move to left or right based upon transistor sizing and voltages on x and y axis depends upon the Vio ).
Also, current is high when one transistor is in saturation and another one in linear. Due to slow charging and discharging of gate capacitance at inverter input in slow slew mode, both transistors conduct at the same time for longer period of time whenever output switches. Hence effective power consumption increases.
Based upon the application, slew rate can be selected. Slow slew rate can be the best option if power consumption is not the highest priority. However, in high frequency communication, high slew rate is the only option.
When forced to use high slew rate, you can avoid EMI by following good layout practices like having the return paths of the signal to be underneath (if possible) or right next to the signal traces.
ESD Protection diodes
Most of controllers/SoCs have electrostatic discharge (ESD) protection diodes on the pins to protect device from electrostatic discharge. This specification must be checked carefully.
Based upon the ESD at the place where product will be deployed, it needs to be made sure that pin’s internal diode can withstand a particularly high voltage for a particular amount of time.
There are different ESD models like industrial model and Human body model. One should make sure that these specs are met. If internal diodes are not capable to handle the required ESD, external diodes must be used. So, while selecting an SoC, one should make sure that pins have ESD protection.
ESD diodes, not only protect the device from ESD, but also adds constraints on voltage applied on the pins. This is why powering the IOs before powering the device is considered damaging.
When device is not powered by the power pins and voltage is connected to IO pins, device is back powered from the pin through the ESD diodes. It can damage the IO cell due to excessive currents flowing through it.
Another question which we quite often get is, can we connect more than rated voltage to IO input? Answer depends upon the spec of the device being used.
(This voltage must not be confused with ESD voltage rating. ESD voltage rating is based upon the particular model which defines the amount of time for which high voltage can be applied ).
The first point to be looked at is, maximum operating voltage of device. The input voltage – forward voltage of the diode must not go beyond the maximum operating voltage of the device.
Another point to be considered is the maximum forward current of ESD diode. If the input voltage causes current higher than this current, an appropriate value of series resistance must be used to limit it.
Though these workarounds can be used, they are not very safe to be used. The second part of this article discusses about capabilities of some devices which allow different pins to have different Vdd supply.
Next in Part 2: Hot swap and other implementation issues.
Sachin Gupta is a Senior Applications Engineer Sr. at Cypress Semiconductor. He enjoys working on different mixed signal applications. He can be reached at email@example.com.
Kannan Sadasivam is a Staff Applications Engineer with Cypress Semiconductor Corp. He has spent a considerable amount of his past career designing and integrating Satellite subsystems. He loves working on different types of analog circuits and applications. He can be reached at firstname.lastname@example.org.