Moore's Law is creating a tsunami of front-end verification complexity in nanometer IC implementations. In the past, Moore's Law primarily impacted hardware verification, stressing existing solutions. Today, however, integration of embedded digital signal processors (DSPs) and microprocessor cores has taken this challenge to a whole new level of complexity. With the integration of these cores, IC vendors are expected to provide not only fully verified hardware, but also the associated hardware-dependent embedded software. Consequently, the critical path to success for DSP and system-on-chip (SoC) developers is through the dual challenge of verifying hardware — already a daunting task — and co-verifying it with the hardware-dependent embedded software.
Historically, the industry has developed a variety of methods for the pure hardware verification flow. The most powerful of these is the use of abstraction and associated tools as a method for solving the right problems at the right level. This approach has led to the migration from layout to RTL, during the last four decades, resulting in significant efficiencies. In fact, a single designer now can build hardware containing millions of gates instead of hundreds, as in the early days. Sophisticated formal, directed-random, and hardware-assisted verification methods also have been added. When these methods are properly used, leading-edge teams can successfully build ICs with first-time success. The key is to invest in tools and methodology early in the design cycle.
In contrast, the software verification flow has not changed significantly during the past 20 years. The number of lines of verified code designed by each software designer today is not much different than in previous years. However, today's significantly larger programs require many more software designers. Embedded software compounds the problem because it can be verified only in the presence of hardware, which is malleable in SoCs. The problem is that the platform for embedded software verification is available only very late in the project cycle, when the hardware is fixed and embedded software is on the critical path. These factors are leading to a crisis in delivery of the whole product to the marketplace.
Resolving these issues likely will require extensive adoption of abstraction and significant investment in verification by embedded software designers early in the design process. Given the need to solve both the embedded software and hardware problem, the abstraction layer must be powerful enough to drive both the embedded software and hardware implementation flows, yet be at a level where significant problems can be resolved at early stages in the design cycle. Use of transaction level models in languages such as SystemC seems to offer an attractive solution, especially if these models can be refined to the RTL level in a coherent environment.
There is a clear and compelling need, therefore, to unify hardware and embedded software approaches, in order to deliver early analysis and verification of chips during the design process.
Rahul Razdan, Ph.D.
Corporate Vice President and Group Manager,
Systems & Functional Verification Group
Cadence Design Systems, Inc.