Bringing experimental development methods to PCB design and manufacturing -

Bringing experimental development methods to PCB design and manufacturing

PCB technologies are undergoing a major new evolution unlike anything the industry has seen before. Issues relating to PCB size, shape, complexity, thermal requirements, and shrinking board space are creating design and assembly/manufacturing challenges for the original equipment manufacturers (OEMs), chip and component makers, material suppliers, and the electronic manufacturing services (EMS) providers. The effort to resolve these issues is changing the dynamics among these key players.

These challenges are pushing PCB design and manufacturing methods to newer levels and are creating demands for more efficient device packaging, newer substrate alloys, and better soldering pastes and fluxes to meet new printed circuit board (PCB) assembly and manufacturing requirements. But the major OEM requirement is for a research and development-like environment within which to conduct experiments to prove or disprove the validity of the new techniques in next-generation embedded systems.

Design of experiments (DOEs)
Consequently, EMS Providers are being called upon to take on the task of ‘design of experiments’ or DOEs, also known as experimental designs, requiring them to work with OEMS to do the necessary research and development. A DOE is an information gathering exercise where variation is the main characteristic. It can be performed as a fully controlled set of experiments, or as a partially controlled set of experiments that involve changing one variable and keeping everything else the same.

For example, it could be the chemical formulation of a flux that’s made differently or it could be different composition of materials. In a specific case, the component of metal balls of the solder powder is different. At times, the acidic level of sulfate in the fluxes is different. This would make it a quasi-experimental design or fully natural experiment in which some of the elements in the design are changed, but others are not.

The objective is to collect as much information as possible by doing the same experiment in a variety of ways to achieve the OEM’s objective. Experimental designs can be used at the point of greatest leverage to reduce manufacturing complexity and introduce new technology. When the prototype is being designed and manufactured, there is some uncertainty about how the design will work and any way to speed up up the process can reduce the time it takes to verify the functionality of the product as well as final time to market. It also reduces the design chain cycle time, product material requirements, and labor complexity. When these changes are made, an advanced type of flux may be used. Simultaneously, the associated thermal profile needs to be adjusted.

Forces driving DOEs
A key driving force for DOEs is the fact that shrinking board space is placing heavy demands on chipmakers to manufacture their devices in smaller, yet efficient packaging. Previously, EMS providers dealt with devices and components in larger packages and device packages with gull-wing leads sticking outside the actual package and onto the board, thus making it easy to assemble and inspect them. There was ample PCB real estate for earlier generation packaging.

But now, leadless packages are used to conserve board space and provide both better performance and improved heat transfer. Also, since board real estate is tapped out, components are stacked on top of each other for a package-on-package (PoP) design arrangement, as shown in Figure 1 . However, when packaging becomes so small, PCB design and layout become highly challenging.

Figure 1: When PCB real estate is at a premium, components are stacked on top of each other for a package-on-package (PoP) design arrangement. (Photo courtesy of MyData Corporation)

Further, as shown in Figure 2 , thieving (or ground pour), the traditional copper overlay on boards to help dissipate heat, cannot be used in most cases with those shrinking PCBs. There’s simply no space left to perform ground pouring.

Figure 2: Thieving or ground pour, the traditional copper overlay on PCBs to help dissipate heat, cannot be used in most cases with shrinking PCBs.

These are only a few samples of the many issues and challenges OEMs face as they move into newer system frontiers. DOEs help resolve them with their varying experiments and successful results.

Pushing the technology envelope
Types of DOEs include, but are not limited to, the following:

  • Crystalizing futuristic technologies
  • Checking out newer solder pastes and fluxes to comply with ever-changing tight ball-grid array (BGA) pitch
  • Resolving anticipated technology issues in subsequent product generations
  • Determining long-term product reliability
  • Evaluating different PCB design and assembly practices to improve product yield

Most often, the common denominator among DOEs is the fact that the OEM is intent on pushing the technology envelope. Working off their imagination, designers know they can design practically any new and innovative product using state-of-the-art electronic devices. However, they also are well aware that there can be manufacturing limitations.

Those limitations involve different processes, physics laws, and different mechanical, electrical, and manufacturing constraints. Still, venturesome OEMs want to explore those frontiers.

Take for example the OEM who figured his LED application would fit nicely in conventional chip on board (CoB) packaging. However, prior to assembly, he learned differently. There were three major issues: board warpage, thermal management, and little to no pad adhesion of the CoB to the PCB’s surface.

The LED/CoB was large, measuring about an inch long. The PCB that the CoB was assembled on was 40 mils thick rather than the regular thicker one of 62 mils. In this case, there was warpage on both the CoB and the PCB itself, even when undergoing a single reflow cycle. The CoB was warping due to its size; the PCB was warping due to its minimal thickness.

Plus, a significant amount of thermal energy the LED generated could not be transferred from the CoB to the PCB and then to the ambient; the heat generated by the CoB was trapped underneath the package. The lack of pad adhesion was due to the tiny 25-mil pitch pads. During printing, as a result of the small size of the pads the adequate amount of solder paste wasn’t being dispensed. Hence, there was no good adhesion although the PCB had an electro-less nickel immersion gold or ENIG surface finish.

The solution was hybrid proprietary BGA (ball-grid-array)-like packaging. In this arrangement:

  • The package has BGA balls situated at the four corners, allowing efficient adhesion.
  • The balls also provide the necessary thermal escape routes to the ambient.
  • BGA-like adhesion to the PCB was properly performed since pads were eliminated and replaced by the BGA balls.
  • Thermal management became considerably more efficient since now there is sufficient BGA ball diameter. That greater area on each BGA ball removes the thermal energy more effectively, and it goes to the PCB’s surface for heat dissipation.
  • Warping is eliminated because the package is more robust.
  • It allows the LEDs to shine from the package’s underside and through a hole created in the PCB.

Another example of DOE is when a very tight BGA pitch is involved. In this instance, another OEM came up with a highly advanced design populated with a number of 0.25 mm pitch BGA devices. Earlier, BGA ball pitch was one millimeter. Subsequently, it got smaller, going to 0.8 mm, 0.5 mm, and finally 0.3 mm. At those geometries, two 5 or 4 mil traces can be run between two adjacent BGA balls. Circuitry can then be cleanly connected without jeopardizing the current load going between those two traces.

However, going to a 0.25 mm pitch is another story. In effect, there’svery little space between two BGA balls for signal traces to run betweenthose two tiny balls. The best that a PCB designer can do is runthinner 2 mil traces between those BGA balls, as shown in Figure 3 . Thedesigner has to be smart enough to know the kind of current load he orshe has to calculate, and the current creepage, capacitance, andinductances associated with those traces.

However, those tracesmay still be questionable for effectively carrying current between thosetwo points. In such cases, the PCB designer tries a different approachand devises a clever and efficient way of fanning out thosetraces. Sometimes that’s not enough. So, as another aspect of this DOE,the number of board layers on the board can be increased to accommodateall the traces coming out of the board.

Figure 3: Running thinner 2 mil traces between BGA balls is questionable, posing potential PCB fabrication issues.

Still,pitch is so tight that no more than one trace can be run between twoBGA balls. That also means automated visual inspection or AOI at PCBassembly is considerably limited since today’s equipment isn’t advancedenough to fully view critical component details. Further, shrinkingboard area and continually smaller packages pose challenges toconventional pick-and-place machines.

The PCB designer is theone who best knows the limitations of a DOE. That includes knowingwhether or not a reputable board fabrication house can successfullyproduce the right PCB, as well as knowing if indeed the advanced designcan be manufactured successfully.

In this DOE example, the finalreport given to the OEM concludes that the advanced design was notpossible from a design-for-manufacturing (DFM) perspective. In effect,performing such a DOE is a way of either validating or invalidating thetechnology the OEM is trying to push the envelope with.

After a DOE is conducted, one of three answers the OEM can expect to hear is:

  • Yes, it can be done.
  • It can be done, but with certain recommendations and changes.
  • Your DOE was well executed, however your effective solution is still out in the future.

Other DOE examples
AnotherOEM wants to know how their product will age in five, ten, and 20years. However, the engineers want to collect that data in a matter ofdays and learn the level of failure. If an IC failure occurs, they wantto know where in the product it occurs. That’s half the deal; the otherhalf is determining the manufacturing steps taken to address that weaklink in the overall failure and address it in the next revision so theproduct doesn’t fail. This can be done by using high-end thermal cyclingchambers.

OEMs also are intent on maintaining high systemreliability for future generations. They understand that smallerpackaging and tighter quad flat-pack no-lead (QFN) and micro BGA pitchdemands the right solder paste and flux. OEMs know they cannot depend ontraditional ones. In those cases, solder flux and paste manufacturersare ahead of the game with newer methodologies to address thoseconcerns. They’re striving for more active fluxes with a finer grain ofmetal content. Paste is a mixture of flux and solder powder. So thecontent of metal in solder powder is finer. The reason for it is it canmore effectively perform soldering on the finer balls within smaller andtighter spaces.

Meanwhile, a chipmaker has come up with using anew alloy to make the lead or pin terminations. The OEM wants to testit and learn how viable it is in manufacturing. The EMS provider may usethe new IC with the new terminations and run a multiple set ofexperiments. Different conditions would be exercised to ascertain howtheir new alloy works under the different set of conditions. Thoseinclude: temperature, heat cycle, reflow conditions, solderingconditions, printing adhesion to the surface, and several otherconditions.

A third example is an LED. The OEM wants to use anew kind of flux and/or alloy for the solder paste. Then the OEMcustomer wants to learn how effectively that LED will undergo assemblyprocesses.

A similar DOE is evaluating an FR4 version of a metalcore board for a newer LED package assembly. In this case, the OEM isinterested in how and how much heat transfers when this board issubjected to different temperature cycles, thermal profiles, and soaklevels. In cases like this, the EMS Provider must collaborate not onlywith the OEM, but also with the solder paste manufacturer to develop theright mixture for this particular experiment.

Each DOE isunique in the sense it is characterized by an OEM’s specialrequirements. However, all DOEs share a variety of different PCB designand assembly aspects and stages such as board finishes, temperaturecycles, thermal profiles, solder pastes, different fluxes, chemicalagents, and so on. DOEs also extend beyond such issues into theextensive nature of PCB cleaning. OEMs are taking an even closer look attoday’s board cleanliness and demanding ultra-clean boards due to newerand smaller packaging and ever-shrinking PCBs.

Medicalelectronics OEMs, in particular, want to avoid product flaws or failuresoccurring due to inadequate PCB cleaning. In some cases, these OEMswant to evaluate conventional de-ionized (DI) water with newer,different chemicals for batch cleaning, test the results, and performionograph testing to determine which cleaning methodology is best fortheir products. This involves recording automatically the state ofionization of the air or of any gas. It consists of an air-condenser,one plate of which is grounded through a high resistance while the otheris connected to an electrometer.

Three-way partnership
Inmost cases, a specific DOE involves not only the OEM and EMS Providerteam, but also the material supplier such as a flux or solder pastevendor. The material supplier, in particular, is key to resolving a DOEbecause a flux or solder paste, for example, can be the deciding factorbetween success or failure of newer components being assembled.

Bismuth-basedsolder paste is an example of a newer product that could be used in aDOE. Its biggest advantage is its low temperature. It reflows at 140°C,which is 47° lower than leaded temperature profile. The lowertemperature means that components on a PCB undergoing reflow avoid beingthermally stressed. Bismuth-based solder paste is especially ideal forthicker 120- to 150-mil thick, 20+ layer PCBs, which require longerreflow time.

What it takes to effectively conduct DOEs
Here’s the information an OEM expects from the EMS provider:

  • The nature of existing problems
  • Availability of common solutions
  • Brainstorming for out of the ordinary solutions
  • On-going controlled experiments changing one variable at a time
  • Repeating these controlled experiments using other variables

Tocomply with those OEM requirements, the EMS provider must haveextensive and detailed experience in PCB design/layout, fabrication, andassembly/manufacturing. Beyond those requirements, management must beinnovative and forward thinking. In some cases, DOEs demand improvising,and in most instances, the success in improvising comes about due toexperience. Successful DOEs also take into account the willingness of anEMS provider’s engineers to invest in experiments of their own at theEMS’ expense and time to figure out a way for the OEM to solve aparticular and troubling issue.

Zulki Khan is theFounder and President of NexLogic Technologies, Inc., San Jose, CA, anISO 9001:2008 Certified Company, ISO 13485 certified for medicalelectronics, and a RoHS compliant EMS provider. Prior to NexLogic, hewas General Manager for Imagineering, Inc., Schaumburg, IL. He has alsoworked on high-speed PCB designs with signal integrity analysis. Heholds B.S.E.E from N.E.D University and M.B.A from University of Iowaand is a frequent author of contributed articles to EMS industrypublications.

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