Bringing programmability to portable design -

Bringing programmability to portable design


This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.

The last decade has seen rapid and permanent change in technologymarkets toward smaller, more portable systems; many large systems thatonce sat on a desktop are now portable, while portable devices thatused to fit in a backpack or briefcase must now fit in a shirt pocket.This has brought many additional design demands, most obviously batterylife. Time between recharging, once measured in hours, must now stretchfor days.

Size and power considerations are now often the top priority in manysystem designs, but portability and long-lasting power can becomeconflicting design requirements. Design teams are continuallychallenged with packing more and more functionality into smaller andsmaller packages, and then somehow squeezing enough power into the samepackage to keep everything running for days, weeks, or even months at atime on a single battery charge.

Meeting size and power requirements in portable devices typicallyrequires application specific integrated circuits (ASICs). Increasedmarket pressures comprising shortened development cycles and lowercost, however, make the time and expense required for ASIC developmenta high design risk. Taking time to design and debug an ASIC could leadto missing ever shrinking market windows, or drive development costs sohigh it�½s impossible to make a profit.

Figure1. Sample FPGA power mode profile based on time spent in mode

So what does a design team do? Field programmable gate arrays(FPGAs) are the answer. In many applications, FPGA functionality rivalsand often surpasses that of an ASIC. But beware: not all FPGAs arecreated equal, especially in portable, low-power applications.

<>While a detailed description of an FPGA is beyond the scope ofthisarticle, a simple explanation will serve our purposes. If you openedthe cover of an FPGA, you would find multiple programmable logic blocksand a network of customizable interconnects.

Design teams program thedevice by connecting logic blocks, via transistors in theinterconnections, to create custom functions. In an ASIC, the functionperformed by the transistors is achieved using fixed, metalinterconnections, defined at the time of fabrication or spin�½.

FPGAs offer design teams two key benefits: design flexibility andfast time-to-market. Using FPGAs, designers can create and testmultiple design options in the time required for a single spin of anASIC design. The result is a better design in a shorter time.

With these important benefits, you might wonder why FPGAs aren'tused in more designs. The answer lies in process technology. FPGAs havetraditionally been fabricated using static random access memory (SRAM)technology which results in a device with a large circuit boardfootprint and high power draw. These drawbacks limit an FPGA's utilityin portable applications. FPGAs based on flash technology overcomethese drawbacks and make programmable logic an ideal solution forportable devices.

Figure2. SRAM power up and configuration current versus nonvolatile flashFPGAs

Actel Corp.'s industry leading low-power flash FPGA technologyovercomes the size and power limitations of SRAM FPGAs. Actel'snon-volatile, reprogrammable flash FPGAs use a single flash cell toform efficient interconnects. Compare this with the six-transistor cellinterconnect used in SRAM FPGAs, which accounts for the largerfootprint and higher power requirements. Actel's nano FPGA devices areavailable in packages as small as 3x3mm with power consumption as lowas 2 microwatts.

Designing with FPGAs, however, is not without its challenges,particularly when developing low-power applications. Designers mustlook beyond device datasheets and consider the FPGA's entire powerprofile. An FPGA's power profile depends on five distinct modes ofoperation: Power-up mode, configuration mode, stand-by mode, activemode, and sleep mode. To determine total power requirements, designteams must calculate how much time the system spends in each mode ofoperation. Operating temperature must also be considered as FPGA powerconsumption varies directly with temperature.

Power-up mode: SRAM FPGAs areusually not configured at start up, a state they remain in until theinitial power-up and reset sequence is complete. The power-up processincludes ramping power supplies to their final value, ramping thesystem to a stable state, and configuring the FPGA based on systemconfiguration information (see configuration mode below).

The power-up sequence can create a current spike of several ampereslasting several hundred microseconds. To moderate the SRAM power-upsurge, design teams often use complex power sequencing techniques,which add more cost and complexity to the system.

With restricted power sequences, standard voltage regulators cannotbe used and more expensive power sequencing devices are required. Alsosince sequences may be different from the standard system voltages, theuse of power planes may be limited as well, adding additional boardlayers. Actel's flash FPGAs feature a very limited power-on currentsurge and no high-current transition period.

Configuration mode: Once thepower-up and reset sequence for an SRAM based FPGA is complete, theconfiguration sequence starts. In configuration mode, the FPGA isconfigured by a bitstream, downloaded from an external device. Theconfiguration sequence can easily consume several hundred milliamps forseveral hundred milliseconds.

This sequence repeats itself every time system power is cycled. Suchpower requirements may be acceptable for systems connected to theelectric utility grid, but they are often unacceptable for portable,battery-operated systems, especially those with limited access torecharging. In contrast, Actel's flash FPGAs retain their programming,even if power is completely removed from the device. The result is noconfiguration cycle power-drain.

Standby mode: An FPGA may spendmost of its time in standby mode, where the device is powered-up butnot active. Power in this mode is commonly called static power. FPGAsare commonly used as co-processing devices, where parallel processingis required for data processing or image manipulation. In systems wherethe device may be waiting for user input, a simple processor canperform basic user interfaces, while waiting for an interrupt toindicate that it is time for the FPGA to power up and performprocessing.

Even in this mode, SRAM FPGAs use significantly more power thanflash FPGAs. Temperature also plays an important role in standby mode.At room temperature, SRAM FPGAs can draw 1000x or more static powerthan flash FPGAs, increasing at elevated temperatures. Even forportable devices that operate mostly in standby mode, flash FPGAs arethe clear choice.

Active mode: Inactive mode, FPGAs perform operations based on their programming. TheI/Os and logic cells are switching, and power consumption (of dynamicpower) is a function of capacitance, operating voltage and switchingfrequency.

If dynamic power were the only power component incurred throughexecuting logic operations, power profiles for all advanced FPGAtechnologies would be similar. But the total power in active modeincludes the dynamic power plus the static power. Even in active mode,SRAM FPGAs consume more power than flash-based devices, because of thesignificantly higher static power component. And as with stand-by mode,the power difference in active mode at high temperatures is even morepronounced.

Sleep mode: To conserve power inportable devices, particularly when idle, design teams commonlyimplement system sleep modes. Note that sleep mode is different fromstandby mode. In standby mode the device is powered-up but is notexecuting instructions; in sleep mode the device maintains only minimumpower levels to ensure quick startup once the system is switched on.

Without special design considerations (such as additional circuitryto compensate for sleep mode) SRAM FPGAs lose their configuration dataand must be reconfigured before switching to standby or active mode;making this switch consumes configuration power.

Actel's flash FPGAs offer low-power modes via their Flash*Freezetechnology. With simple single-pin Flash*Freeze activation, Actel'sIGLOO nano FPGAs consume as little as 2 microwattss of power in sleepmode. Most SRAM FPGAs do not offer comparable modes, however oneexample does reduce static power from 350mW down to 200mW in suspendmode.

In the portable marketplace, low-power technology is of little usewithout small scale packaging. Device footprint and thickness areimportant, as is the number of I/Os. Actel offers device footprints assmall as 3x3mm with thicknesses down to a very thin 0.7mm, the smallestform factors in the industry. And by using micro chip scale technologywith 0.4mm pitch packaging, Actel leads the programmable logic marketin per device small scale package I/O.

Fast moving technology markets are forcing designers to replaceASICs with flexible FPGA technology to reduce design time and risk.Choosing the right FPGA technology is critical to design success in theportable, low-power market. SRAM FPGA's large device footprint and highpower requirements make them unsuitable for these applications.

Actel's nano FPGAs enable programmable logic use in this fast movingmarket with device footprints as small as 3x3mm and power up to 1000times lower than SRAM FPGAs in active, static and sleep modes. Finallydesigners have a realistic programmable alternative to ASIC technology.

Wendy Lockhart is pricipal engineerat Actel Corp.

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