Broadcom is now sampling what it claims is the world’s first high definition Ultra high definition television decode, the BCM7445.
Demonstrated at CES 2013 this month, at the core of the chip is its implementation of the just released successor to the H.264 video spec, the High Efficiency Video Coder (HEVC), also known as H.265.
According to Dan Marotta, Broadcom's Executive Vice President and General Manager, Broadband Communications Group, the 28 nm, ARM-based BCM7445 is the first step to delivering UltraHD TV into the home with the performance and picture quality needed for the evolution in multi-screen connected home entertainment.
UltraHD TV technology, formerly known as 4K, is designed to display four times the resolution of today's 1080p60 displays. As a result, he said, the delivery of UltraHD TV requires a more efficient compression codec.
This was made possible by the use of the new HVEC standard, which speeds Internet video downloads giving operators and users the ability to download content such as movies in half the time and with higher quality video at 50 percent of the bit rate previously required.
“The clarity and brilliance of UltraHD television is a significant step forward in viewing enjoyment and is the next true evolution in TV innovation,” said Marotta, pointing out that HEVC, which will be known as MPEG-5 or H.265, will allow faster IP downloads and the provisioning of VoD services over wireless networks.
In addition to the HEVC technology, the chip also incorporates the company’s Brahma15, and SoC that incorporates a 21,000 DMIP CPU, four 1080p30 real-time transcoders to deliver resolutions up to 4096x2160p60.
The BCM7445 also features web domain security, an industry leading hardware security mechanism that separates Internet services from premium broadcast content. This protects critical core network functions from malware threats, paving the way for operators to securely converge and deliver pay-TV programming and open Internet applications to subscribers for a web-based TV experience.
The Brahma15 is a Quad-core ARMv7-A instruction set compatible Multiprocessor in which 32KB instruction and 32KB data caches per processor are backed by a shared 2MB L2 cache and feed the multi-issue, out-of-order superscalar 15-stage plus write back pipeline.
A 32KB read-ahead cache between the L2 cache and the memory controllers provides 8KB of read latency reduction per processor. The Brahama15 supports the ARM Trust Zone security architecture, software virtualization and hardware virtualization by core for complete security isolation.
Each core individually supports single cycle ARM NEON 128- bit vectors for software based media processing applications. The entire architecture supports Broadcom's Nexus and Trellis software interfaces.