PCI Express and the Hunger for Bandwidth
As a means of connecting computing, embedded and custom host processors to ‘end-point’ peripherals such as Ethernet ports, USB ports, video cards and storage devices, PCI Express® (PCIe®) has become the reference high-performance interconnect. Leveraging high-speed serial communication, PCIe delivers efficient point-to-point connectivity and – by increasing channel count and signaling rate – scalable interface bandwidth.
The PCIe 1.0 specification was published in 2002, operating at 2.5 giga-transfers per second (GT/s) giving a total x16 interface bandwidth of 8GByte/s. The bandwidth was subsequently doubled in 2006 with the arrival of the second-generation PCIe 2.0 specifications and again in 2010 when PCIe 3.0 raised bandwidth to 32GByte/s to meet ever-increasing demands imposed by leading contemporary applications including high-end PC, gaming, enterprise computing, and networking.
PCI Express has become the reference high-performance interconnect for a wide range of system designs.
(Source: Diodes Inc.)
More recently, the rapid spread of cloud-based services such as social media and video streaming has introduced new and more demanding requirements for high-speed connectivity within large-scale data centers.
Now, as the IoT era takes hold, networked sensors installed throughout smart cities and infrastructures, smart factories and other industrial assets, commercial and residential buildings, and wearables for fitness and medical tracking are set to generate vast quantities of data for hyperscale data centers to capture, store, process, and analyze. These forces are driving demand for the next PCIe generations to efficiently connect data-center servers to high-speed Ethernet, network-attached storage, and AI accelerators.
Connected cars will further increase the data load, adding real-time pressure, to enable higher levels of autonomous driving and ultimately full self-driving vehicles. Behind the data centers, training neural networks for AI inference is a compute-intensive task that sharply exposes bottlenecks in peripheral communications.
As these various factors now come into play, the time is right for PCIe to move forward again. PCIe 4.0, announced in 2017, was quickly followed with the publication of PCIe 5.0 in 2019. Figure 1 shows the aggregate speeds offered by each PCIe version.
Figure 1: Aggregate speeds offered by PCIe versions (Source: Diodes Inc.)
PCIe 5.0 is expected to become widely used as leading data centers make the transition from 100Gb Ethernet to the latest 400Gb specification. In practice, increases in PCIe bandwidth have more or less kept pace with advances in Ethernet speeds, ideally keeping a balance between the two standards to help avoid performance bottlenecks.
“Legacy” PCI Standards Remain Current
As PCIe 5.0 products start to enter the market, and with the recent announcement by the PCI Special Interest Group (PCI-SIG) that work has commenced on the next generation, PCIe 6.0 for completion in 2021, PCIe is the protocol of choice for performance-hungry peripheral communications, for the foreseeable future.
At the same time, backwards compatibility is a key strength of the PCIe lineage. Because there is no expiry date for PCIe specifications, several generations can coexist in the marketplace and even in the same application. This is an advantage for system designers: while successive new PCIe generations emerge to address increasingly bandwidth-hungry requirements, earlier iterations continue to deliver value in a large number of scenarios such as personal computing, gaming, and some enterprise computing and networking applications.
Solving Implementation Challenges
Backwards-compatibility between the various PCIe generations enables systems to benefit from higher transfer speeds as new silicon becomes available, with minimum design changes. On the other hand, rising signal speeds place extra pressure on signal margins and can increase design complexity. In addition, there is a clear need for solutions that enable bridging to and from PCIe, not only between legacy interfaces but also other interfaces such as USB or graphics ports.
To handle these challenges, designers need access to devices that support various PCIe generations, such as the clock generators, clock buffers, controllers, packet switches/bridges, ReDriver™ chips, and high-speed multiplexers shown in figure 2.
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Figure 2: An example of the PCIe solutions available from Diodes Inc. (Source: Diodes Inc.)
ReDriver chips can provide a cost-effective and convenient solution for boosting signal integrity in high-speed systems. Using techniques such as equalization and pre-emphasis, with an output driver that introduces minimal latency, the ReDriver compensates for transmission-line losses to restore signal margin and minimize jitter to ensure a low bit-error rate at the receiver. Compared with a retimer, which integrates additional functions including clock and data recovery, a ReDriver introduces low delay and is relatively economical and easy to implement. Figure 2 shows how a PCIe ReDriver may be used where signals are required to be driven across a longer PCB track, such as to an external graphics card or via cable to external storage. These ReDrivers are fully backwards compatible, supporting all previous PCIe generations.
Bridges and switches satisfy requirements to interface between host and endpoint devices of various types. A packet bridge will typically provide an interface between two layers in the OSI reference model, or between two protocols. Figure 2 also shows how a bridge can be used to connect between PCIe and legacy PCI standards including PCI-X, or to USB ports or a UART bus interface. Packet switches are multiport/multilane devices typically used to expand a single root complex to several ports with multiple lanes for accessing other peer systems such as a peripheral or line card.
In addition to individual packet bridges and switches with various port configurations and translation capabilities, the functionalities of a PCIe packet switch and PCIe-to-USB2.0 bridge are combined in devices such as Diodes Incorporated’s PI7C9X442SL PCI Express-to-USB 2.0 ‘swidge’. This multi-functional device can fan out from one PCIe x1 upstream port to two x1 downstream and four USB 2.0 ports, and lets the system host processor access multiple PCIe and USB devices simultaneously.
Companies such as Diodes Inc. can offer a portfolio of passive bidirectional PCIe 1.0, PCIe 2.0, or PCIe 3.0 signal multiplexers/demultiplexers to connect a single PCIe lane to multiple lanes for bandwidth expansion for graphics or computation. These devices can also be used for enabling connections from a single multi-protocol interface.
Clock buffers can typically take a single reference signal as an input and produce multiple outputs for wider distribution around a PCB. Clock buffer ICs are available in a variety of configurations and Diodes offers a proprietary PLL design that ensures jitter remains well within PCIe requirements. Clock generators can generate a clock signal at a specific frequency with very low output jitter, making them suitable for PCIe as well as other system clocks. Designers can find a wide range of suitable devices such as Diodes’ 1.8V PI6CG18xxx and 1.5V PI6CG15xxx PCIe 4.0 clock generators and buffers in 2-, 4-, and 8-channel configurations, which are compliant with all previous PCIe generations. By integrating terminations on-chip these devices save four external resistors per output, trimming up to 32 components from the bill of materials.
PCIe is the go-to high-performance interconnect for applications from embedded and desktop computing to high-bandwidth data-center connectivity and neural-network training. Designers can take advantage of the long useful life of earlier PCIe standards, with backwards compatibility between legacy and later-generation specifications, to satisfy diverse system requirements cost-effectively. With access to a device portfolio containing functions such as bridges, buffers, ReDrivers, switches, and mux/demux ICs, designers can deliver efficient solutions to demanding applications.
|Kay Annamalai is Senior Marketing Director at Diodes and specializes in high-speed signal integrity products. A 30-year semiconductor industry veteran, Kay holds several patents and has published in conferences and technical journals as well as contributing to the establishment of several physical layer standards. He holds a BSc in electronics and communications engineering from Madras University and an MS in electrical and computer engineering from UC Santa Barbara.|