Building quality & signal integrity into PoP-based PCB design & assembly - Embedded.com

Building quality & signal integrity into PoP-based PCB design & assembly

Editor's note: This article addresses the need for designers of printed circuit boards for nextgen ICs to be savvy about package-on-package technology.

New ways of working with sub-assembly printed circuit board (PCB) design and assembly have become necessary to design effectively for the new era of package-on-package (PoP) technology. Following the new design guidelines and assembly procedures for high density ICs fabricated with nanometer-scale geometries will assure that an OEM’s product will meet its performance objectives.

There are multiple factors involved, and each plays a significant role in efficiently designing and assembling PoP-based PCBs. Among them are high reliability, excellent signal integrity, design for assembly (DFA), and state-of-the-art pick and place on the assembly floor.

At the Trace Level
Maintaining high reliability for BGA-based PoP board design starts at the trace level. A good guideline to follow is to have only one trace between two BGA pads because two traces pose manufacturing difficulties. Also, board fabrication challenges arise when running multiple thin 2-to-3 mil traces between two BGA pads. Further issues surface if the length of those thin traces is too long, and if those types of traces are spread throughout the board.

Ideal traces are 5 mils or thereabouts. Generally, they are highly acceptable as good manufacturing practice. However, in today’s world of miniaturization, those 5 mil traces may not be practical or possible. In the small PCB world requiring PoP, high reliability and excellent signal integrity demand that a single trace be no more than 2.5 to 3 mils between BGA pads, as shown in Figure 1 .

Figure 1: High reliability and excellent signal integrity demand that a single trace be no more than 2.5 to 3 mils between BGA pads.

Other design factors include blind vias, solid ground planes, and decoupling capacitors. Buried vias are to be avoided as much as possible. Blind vias are okay to use because they are easier to work with during manufacturing. On the other hand, buried vias are difficult because they require one further lamination cycle. Also, it’s important to use solid ground planes as much as possible to maintain ultra-clean noise suppression and keep signal-to-noise ratio (SNR) under control.

As shown in Figure 2 , keeping decoupling capacitors as close as possible to BGA balls holds true with PoP more than ever before for high signal integrity, especially if a high speed layer is involved. The PCB designer needs to make sure decoupling capacitor distance between the capacitor and the BGA ball is as short as possible, keeping signal distance between points A and B as short as possible.

Figure 2: Decoupling caps placed closed to the BGA pins in a via-in-pad design

One decoupling capacitor can support up to three BGA balls. The PCB designer needs to make sure there are enough decoupling capacitors to assure all of them are properly decoupled. If sufficient decoupling capacitors aren’t available, the probability increases of getting a signal considerably noisier and more out of control than expected.

Tracking PoP Through Assembly
Standard operating procedure for the PCB designer is to take the lead in anticipating unforeseen issues that his or her design can encounter at assembly. Early on, the savvy designer works to avoid such issues, and, collaborating with assembly engineering, tracks them so that manufacturing steps are performed without troublesome and costly glitches. With a PoP-based PCB design, this phase is especially critical. The ultimate goal is to make these PoP assemblies reliable, repeatable, and also make certain that the project can be successfully transferred from prototype to production level.

Pick and place is especially important for the PCB designer, particularly the dip unit and the mount head used for PoP placement accuracy – for example, the scatter chart in micrometers. Figure 3 shows the result of a placement accuracy measurement on a MYDATA pick and place machine.

Figure 3: Scatter Chart (Image courtesy of Micronic MYDATA AB)

Each dot represents the deviation from nominal position in x and y for one placement. The dotted rectangle represents the specification limit corresponding to Cpk=1.33, and the two dotted lines represent the average offset. The result is obtained by placing glass slug components with a BGA pattern on a glass plate, and then measuring the position of each component in a Nikon measurement machine.The characteristics of a dip unit are key considerations during theearly phases of design because it is crucial for perfect PoPassemblies. Consequently, it is of utmost importance to the OEM.

Thedip unit is used to apply the correct amount of tacky flux or pasteused in the PoP placement operation. For example, MYDATA’s dip unit isfully automated with no manual adjustments needed. During thepre-production phase, the amount of flux or solder needed is verified,which is relatively easy for automated dip units, but slightlychallenging for manual ones.

Also, the amount of tacky flux orsolder paste must be consistent. The dip unit must deposit the sameamount of paste or tacky flux to uniformly adhere to every BGAball. Bridges or shorts are created when too much flux is used, whereasopens and cold solders appear when too little is used. As for thedipping depth, the normal range is 50% to 66% of the height of the ballfor a time interval or dwell time of 0.1 to 1.0 seconds. For paste, itis about 50% of the height of the ball; whereas for flux, it is 66%.

Anideal dip unit is flexible enough to allow automatic changes in flux orpaste thickness and provides support for different flip-chip bumpsizes. These product traits are especially valuable to stay ahead of anever-evolving PoP technology.

Moving To Next PoP Generations
Theindustry will face challenges as it moves into newer generations,meaning 0.4mm pitch BGAs and below, with PoP stacks of more than twoBGAs. The challenges of PoP assembly in a pick and place (P&P)machine are basically found in two distinct and independent processsteps: solder paste application and placement.

It is importantto emphasize that all major fluid suppliers have developed paste andflux optimized for the dipping process. This means that a thin layer canbe applied on a flat surface using a squeegee or something similar. Forexample, experience shows that the MYDATA Dip Unit works well withcommercially available fluids, doesn’t require a customized fluid, andworks equally well with both tacky flux and dip paste. MYDATA hasexperience with both types of fluids. The conclusion is that the basicmechanical design with a transfer plate with cavities and a squeegee is agood solution for both applications.

As for the secondindependent process step, for a P&P machine to be able to place aPoP device, it must fulfill some basic requirements, such as accuracy,programmable z-level, and post-dipping vision recognition.

High-endP&P machine suppliers shouldn't have any major issues with thesebasic capabilities. However, they may have chosen different approachesin handling the varying z-level. For a more robust PoP process that canhandle larger variations in part height, a fast z-level impact sensor onthe nozzle is preferred, compared to force feedback using servo motorcurrent sensing.

If the placement process is well within thecapabilities of today’s high-end equipment, the paste application iswhere different solutions can have a large impact on the results. Theprocess window is quite small for a successful paste application usingthe dipping method.

A dipping depth of 50-66% of the ball sizeis a typical requirement for BGA type components. It's obvious that thisis hard to reach with a process that is relying on mechanicalproperties of a complex fluid such as solder paste.

In addition,even small variations — for example, part co-planarity, ball size, andoperator skills — can jeopardize quality. These difficulties will beeven greater when going to next-generation PoP with smaller pitch andball size. To stay on the short-list for PoP assembly, equipmentsuppliers must provide a solution that is operator independent and asforgiving as possible regarding material variations.

Second/Third Generation PoP Placement
Thepopular belief is that a pick and place machine requires certainadvanced features and attributes to effectively handle second and thirdgeneration PoP placement. However, that’s a faulty assumption.

Firstof all, when designing an efficient PoP assembly process, it’simportant to look not just at the pick and place machine, but the entireline. Savings in one step may incur additional costs in other steps, soa holistic view is required. The next generation of PoP will certainlydemand higher levels of accuracy and reliability from pick and placemachines, but the industry is facing an even bigger challenge when itcomes to the paste application.

The future development of PoPdevices heavily depends on the equipment vendor’s ability to developsolutions for highly reliable paste application with outstanding volumerepeatability. When placing fine-pitch BGAs with thousands of balls,even a very small increase in defect rate will quickly become a majorissue on final assembly level.

The most critical parameteraffecting overall yield is the volume control or how much paste isactually transferred to each ball. Not only the absolute volume, butalso the ball-to-ball variation is important to understand. Too muchvariation will lead to an open circuit, or even worse, an inferior jointor latent defect that fails later in the field.

The dippingprocess has inherent difficulties dealing with volume control. The pastetransfer is relying on hard-to-control parameters such as tackiness andpaste surface flatness. Also, it is important to note that post-dippinginspection of paste volume is probably not even possible with the typeof 2D vision systems that are generally built into today's P&Pmachines. 3D inspection from below could be a way to take the dippingprocess one step further, but it's likely that the next-generation PoPwill force the industry to look for alternative paste applicationmethods.

One such method could be to deposit paste on the bottomcomponent, prior to placing the top component. The main candidates forsuch a process are dispensing and jetting. While volume control andaccuracy are probably more or less comparable, jetting would have theadvantage of higher speed, making it the preferred choice in high-volumemanufacturing.

Besides the improved volume control, both thesemethods also allow for 3D inspection of the paste deposit prior toplacement of the top component. In-depth studies on the process yieldare needed to determine if such a mid-process inspection will actuallybe necessary to reach the industry's quality requirements.

Zulki Khan is the Founder and President of NexLogic Technologies, Inc., San Jose,CA, an ISO 9001:2008 Certified Company, ISO 13485 certified for medicalelectronics, and a RoHS compliant EMS provider. Prior to NexLogic, hewas General Manager for Imagineering, Inc., Schaumburg, IL. He has alsoworked on high-speed PCB designs with signal integrity analysis. Heholds a B.S.E.E from N.E.D University and an M.B.A from University ofIowa and is a frequent author of contributed articles to EMS industrypublications.

Mattias Jonsson is Product Manager inthe SMT Business Unit at Micronic Mydata AB, Stockholm, Sweden.Micronic Mydata develops and manufactures equipment for SMT assembly, aswell as laser-based pattern generators for manufacturing of displays,substrates and semiconductors. He has also held positions in ElectricalDesign and Project Management. He holds an M.Sc. degree in ElectricalEngineering from the Royal Institute of Technology (KTH) in Stockholm.

2 thoughts on “Building quality & signal integrity into PoP-based PCB design & assembly

  1. This is depends on Impedance used for signal track and used new PoP BGA in upcoming time. Than used high clock signal Which affect to design reliability so we need to analysis on this high speed design we plans pre-analysis which covers before routing on b

    Log in to Reply
  2. about SI analysis any body can suggest me analysis on Connector in PCB.

    what i need basic inputs for the analysis when i have two ICs which is connected through One connector and i want to analysis IC1 to IC2 with connector.

    please suggest to me or if yo

    Log in to Reply

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.