C-code parallelizer for heterogeneous multicore chips - Embedded.com

C-code parallelizer for heterogeneous multicore chips

Compaan Design announced it has released HotSpot Parallelizer for ISO C, supporting x86-multicore runtime verification and Xilinx FPGA code generation.

This product integrates the company's parallelization, streaming and mapping technology with ACE's industrial quality CoSy compiler development framework. The HotSpot Parallelizer translates C-code hotspots to data streaming Kahn Process Networks (KPN) that robustly and efficiently utilize highly parallel heterogeneous multicore chip architectures.

The workflow guides step-by-step parallelization towards improved energy efficiency and computational throughput. Parallelism is exploited for streaming data and increased architecture utilization.

After creating a workflow baseline by compiling to a single-threaded processor, an exact dataflow analysis guarantees correctness and robustness of application execution, says the tool vendor.

It traces all data dependencies and generates a KPN with a FIFO for every individual data flow. KPN nodes and FIFOs are mapped to SW or HW resources. The automatic stub generation lets different subsystems synchronize and communicate.

With the product already in use by several early adopters, the company acquired technical feedback and application experience and boasts huge time savings for VHDL designs. The Compaan Design tool works entirely in tandem with 3rd party C-to-VHDL tools by integrating accelerated functions into an automatically generated system communication framework.

Courtesy of EE Times Europe .

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