The recent Embedded.com article, The Art of FPGA Construction, does an excellent job of demystifying the FPGA development process, using hardware description languages (HDLs) and other methods. I would like to extend this discussion by describing some recent extensions in software-to-hardware tools and propose that these tools are complementary to existing, HDL-based methods of design.
When low-cost, commodity FPGAs broke through the million gate level a few years ago, they became serious contenders for processing intensive embedded applications. FPGA devices today that sell for under $10 in large quantities are capable of integrating complete embedded systems including RISC processors, custom hardware accelerators, processor peripherals, and on-chip memories, all on one programmable device.
The highest-density, newest-generation FPGAs with multiple millions of available gates provide enormous processing power relative per watt of consumed power, when compared to server-class processors. In fact, the largest available FPGAs are now deployed for high-performance computing applications, in areas as diverse as medical image processing, life sciences, and financial computing.
In such environments, the traditional methods of programming FPGAs using HDLs or schematics are hitting some natural hurdles. Application developers creating highly parallel, pipelined algorithms and systems may or may not have the skills, time, or inclination to use hardware-oriented design methods. For this reason, software-to-hardware design tools and methods are increasingly being added to the application designer's toolbox.
In the world of embedded systems, many products already include one or more FPGAs as part of their design, often used alongside discrete processors, DSPs, and other components. Embedded system design teams doing value engineering of such applications have strong motivation to integrate the software aspects of the system (represented by the processor and/or DSP) into a higher density FPGA. The consolidation of such systems into one device can be an engineering challenge, but recent advances in FPGA platform building tools (such as Xilinx Platform Studio or Altera SOPC Builder), coupled with advances in software-to-hardware tools (such as Impulse C and others), simplify this process.
In such an integrated system, software applications running on the embedded processor can communicate directly with application accelerators running as hardware in the FPGA fabric. Tools such as Impulse C allow the hardware accelerator to be described in C, then optimized and generated as hardware processor peripheral, reducing or eliminating the need to write low-level HDL. The advantages of this approach include faster time-to-prototype, more opportunities for experimentation (for example, with alternative hardware/software partitioning methods) and faster, more efficient product deployments.
I'm not suggesting that HDL design methods are obsolete. Quite the contrary, as FPGAs are applied with greater and greater levels of system integration, there's still a need for hardware design tools and methods at the margins of the applications, such as when describing I/O or when creating custom memory interfaces. Certain algorithms (such as low-level control logic) may also be easier and more efficient to implement using HDLs. We can therefore expect that HDLs and software-based approaches will coexist for quite some time.
Of course, the process of moving from software development for traditional processors, to software/hardware development using FPGAs does bring with it some challenges. C code originally intended for a standard microprocessor is optimized for serial processing, and has probably been hand-optimized for the characteristics of that target, for example to make most efficient use of memory. When moving such an application to the FPGA as a mixed software/hardware algorithm, there will be a certain amount of refactoring required to take advantage of the FPGA resources and make the best use of hardware-level parallelism. The good news is that these types of optimizations can now be accomplished in the context of C-language programming, without requiring intimate knowledge of the FPGA hardware.
A good example of this is using C to describe highly parallel, pipelined video filters. In this type of application domain, the FPGA can offload the performance bottlenecks (such as smoothing or noise-reduction filters) while the embedded processor handles less compute-intensive functions. Using a C-to-hardware method of design allows specific C-language subroutines to be more easily moved to FPGA hardware equivalents, while still being validated using standard C-language debugging tools.
In conclusion, HDLs are great for hardware-oriented FPGA design, and will remain the preferred method of entry for the majority of such applications for the foreseeable future. Emerging C-to-hardware tools complement and extend the reach of HDL tools, by allowing software application developers to be part of the FPGA design process. This extends the potential applications for FPGAs, which of course attracts even more software-oriented FPGA designers. A virtuous cycle indeed.
David Pellerin is the CTO of Impulse Accelerated Technologies. He has spent over 25 years in the programmable logic industry and has published five books on the subject of PLDs, FPGAs, and related technologies. Mr. Pellerin earlier founded Accolade Design Automation, where he was the architect of the PeakVHDL and PeakFPGA advanced products for HDL-based FPGA design. He can be reached at .