Cadence and UMC collaborate on certification of analog/mixed-signal flow for 28HPC+ process

Certification enables customers to leverage the integrated, comprehensive AMS solution to facilitate accelerated designs on UMC’s most ad Cadence analog/mixed-signal IC design flow has achieved certification for UMC’s 28HPC+ process technology. With this certification, mutual Cadence and UMC customers have access to a comprehensive AMS solution for designing automotive, industrial internet of things and artificial intelligence chips using 28HPC+ technology. The complete AMS flow, based on UMC’s Foundry Design Kit, includes an actual demonstration circuit with a highly automated circuit design, layout, signoff and verification flow that enables more seamless design on 28HPC+.

The Cadence AMS flow incorporates the proven custom/analog, digital and verification platforms, and supports the broader Cadence Intelligent System Design strategy, accelerating SoC design excellence. The AMS flow features integrated standard cell digital capabilities that are well suited for digitally assisted analog designs, and is an ideal solution for customers developing automotive, industrial IoT and AI applications using the 28HPC+ technology.

The complete, certified AMS flow includes the Virtuoso Analog Design Environment (ADE), Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso Space-Based Router, Spectre Accelerated Parallel Simulator (APS), Spectre AMS Designer with integrated Xcelium Parallel Logic Simulation, Voltus-Fi Custom Power Integrity Solution, Innovus Implementation System, Quantus Extraction Solution and Physical Verification System (PVS). The flow provides the following:

•            Front-end design: Provides corner, statistical and reliability simulation; circuit and device checks; and analog and mixed-signal simulation and verification management.

•            Custom layout design: Offers an advanced, electromigration and parasitic-aware environment that includes schematic-driven layout and module generation, wire-editor and pin-to-trunk routing, symbolic placement, electrically aware design and voltage-dependent rules.

•            Post-layout parasitic simulation and electromigration and IR drop (EM-IR) analysis and integrated signoff: Includes parasitic extraction, DRC, and layout versus schematic (LVS) checks.

•            Mixed-Signal OpenAccess: Enables full interoperability between the Virtuoso and Innovus platforms operating on a single OpenAccess design database, enabling mixed-signal designers to seamlessly perform digital block implementation using Innovus tools directly from within the Virtuoso cockpit.

UMC's production-ready 28HPC+ process utilizes a high-performance High-k/Metal Gate stack to support broad device options for increased flexibility and performance requirements, targeting a wide range of products such as application processors, cellular basebands, Wi-Fi, DTV/STB, mmWave, etc. The High-k-/metal gate stack and abundant options for core device Vt, various memory bit-cells and under drive/overdrive I/O capabilities help SoC designers realize unmatched cost, performance and battery life.

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