Cadence Design Systems announced the availability of the industry’s first Verification IP (VIP) in support of the new DisplayPort 2.0 standard. The Cadence VIP for DisplayPort 2.0 enables designers to quickly and thoroughly complete the functional verification of their mobile, Audio-Visual and AR/VR SoC designs with less effort and greater assurance that the design will operate as expected.
The latest Cadence VIP for DisplayPort 2.0 has been architected to meet the specifications of the new standard—enhancing design verification productivity, ensuring high-quality designs and delivering maximum performance. The Cadence VIP for DisplayPort 2.0 offers the industry’s most comprehensive protocol validation solution for DisplayPort designs and includes a configurable bus functional model (BFM), a protocol monitor and a library of integrated protocol checks to optimize verification predictability. Additionally, the VIP has been designed for easy integration into testbenches at IP, SoC and system levels, helping engineers reduce time to first test and accelerate verification closure.
The Cadence Verification IP portfolio, including the latest VIP for DisplayPort 2.0, is part of the broader Cadence Verification Suite and is optimized for Xcelium Parallel Logic Simulation, along with supported third-party simulators. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments. The Cadence Verification IP supports the company’s Intelligent System Design strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.