Cadence delivers portable test and Stimulus methodology and library

Cadence Design Systems announced delivery of the Accellera Portable Test and Stimulus Specification (PSS) 1.0-compliant implementation of the Cadence Perspec System Methodology Library (SML) and methodology documentation. This new PSS methodology and library was checked by AMIQ using their DVT Eclipse IDE to confirm the new library is PSS Language Reference Manual compliant.

The PSS methodology library enables Cadence Perspec System Verifier customers to access PSS source code for any of the SML functions to develop their models, saving them a minimum of eight weeks of development versus manual library creation. In addition, Cadence will also provide the library in source form along with the methodology documentation to non-Perspec users to help promote the adoption of the PSS. For more information on the Cadence Perspec System Verifier and the PSS methodology and library, please visit www.cadence.com/go/PSSMethodology.

The PSS methodology document and library are accessible via download, providing customers with the flexibility of increased automation capabilities and platform portability. The methodology and library features include:

•            PSS model library: Users gain access to a compliant PSS model library for common processor actions and memory operations.

•            Guidelines for PSS model packaging and adoption: Users gain access to a directory and naming and packaging guidelines that make PSS-reusable code more consistent and easier to package and share.

•            Fully explained patterns and code examples for PSS modeling: Users have access to a dictionary of patterns that they can review and customize to solve their specific needs. Additionally, the patterns demonstrate PSS model reuse and extensibility, allowing platform portability and vertical reuse.

The Perspec System Verifier improves system-level test productivity by up to 10X. It is part of the Cadence Verification Suite comprised of best-in-class core engines, verification fabric technologies and solutions that increase verification throughput. Together, they support the company’s Intelligent System Design strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

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