Cadence enables multi chiplet design with Integrity 3D-IC platform - Embedded.com

Cadence enables multi chiplet design with Integrity 3D-IC platform

New platform provides single unified cockpit to help system-level designers plan, implement, and analyze any type of stacked die system to give a full system view and perform system-driven optimization of performance, power, and area (PPA).

Cadence Design Systems has launched a new integrated 3D design planning, implementation and system analysis platform to enable heterogenous multi chiplet 3D-stacked design.

Its Cadence Integrity 3D-IC platform addresses new challenges arising from the use of advanced packaging techniques such as 3D chip stacking by designers creating hyperscale computing, consumer, 5G communications, mobile and automotive applications.

The new platform provides a single unified cockpit to help system-level designers plan, implement, and analyze any type of stacked die system with a variety of packaging styles, to give a full system view as well as carry out system-driven optimization of performance, power, and area (PPA) for chiplets and co-design of interposers, packages, and printed circuit boards for 3D-IC applications. It allows chip designers to achieve greater productivity when compared to design using a disjointed die-by-die implementation approach. It provides system planning, integrated electrothermal, static timing analysis (STA) and physical verification flows, enabling faster, high-quality 3D design closure.

It also incorporates 3D exploration flows, which take 2D design netlists to create multiple 3D stacking scenarios based on user input, automatically selecting the optimal, final 3D stacked configuration. The platform database supports all 3D design types, letting engineers create designs at multiple process nodes simultaneously and perform seamless co-design with package design teams and outsourced semiconductor assembly and test (OSAT) companies that use Cadence Allegro packaging technologies.

Vinay Patwardhan - Cadence
Vinay Patwardhan

In a briefing with embedded.com, Vinay Patwardhan, product management group director for Cadence, said, “The majority of customers we are engaged with are hyperscale companies exploring 3D packaged ICs. The challenge is that there’s a large demand to move data around, but in the advanced process nodes we’re reaching the physical transistor size limit.” Hence, he said going to the third dimension, or 3D, is a good solution to address this, since it provides shorter wires, uses less power, has a smaller profile and better yield, plus it can address the higher performance and bandwidth requirements.

However, the challenges with 3D chip design are issues such as die placement and bump planning, SoC and packaging teams working in silos, and there’s no single database to represent multiple technologies. Additional system level verification is another challenge, for example thermal analysis from across chiplets, 3D STA becoming a challenge with the explosion of the number of corners for signoff, and inter-die connectivity validation at the system level.

Current solutions are disjointed, point solution based, with a lot of file passing back and forth, and there isn’t a way to do exploration or provide early feedback. The result is costly overdesign of individual dies in a stack.

This is where the company’s Integrity 3D-IC platform comes in, according to Patwardhan. The platform has the following key features and benefits:

  • Common cockpit and database: SoC and package design teams can co-optimize the complete system concurrently, allowing system-level feedback to be incorporated efficiently.
  • Complete planning system: incorporates acomplete 3D-IC stack planning system for all types of 3D designs, enabling customers to manage and implement native 3D stacking.
  • Seamless implementation tool integration: provides ease of use through direct script-based integration with the Cadence Innovus implementation system for high-capacity digital designs with 3D die partitioning, optimization and timing flows.
  • Integrated system-level analysis capabilities: enablesrobust 3D-IC design throughearly electrothermal and cross-die STA, which allows early system-level feedback for system-driven PPA.
  • Co-design with the Virtuoso Design Environment and Allegro packaging technologies: allows engineers to seamlessly move design data from Cadence analog and packaging environments to different parts of the systemthrough the hierarchical database, enabling faster design closure and improved productivity.
  • Easy-to-use interface: includes a powerful user cockpit with a flow manager that provides designers with a uniform, interactive way to run relevant system-level 3D system analysis flows.
Cadence 3D integrity-diagram
New Cadence Integrity 3D-IC platform provides system planning, integrated electrothermal, static timing analysis (STA) and physical verification flows, enabling faster, high-quality 3D design closure. (Source: Cadence)

Chin-Chi Teng, senior vice president and general manager in the digital & signoff group at Cadence, said, “With recent developments in advanced packaging technologies, we saw a need to further build upon our successful 3D-IC foundation, providing a more tightly integrated platform that ties our implementation technology with system-level planning and analysis. As the industry continues to move toward different configurations of 3D stacked dies, the new Integrity 3D-IC platform lets customers achieve system-driven PPA, reduced design complexity and faster time to market.”

Challenges in developing a common integrated platform

We asked Patwardhan about the challenges in developing the Integrity 3D-IC platform. He highlighted three key areas. “The first is that it’s hard to find expertise with the full flow, so we had various teams come together to work on the integrated common platform. The second was in creating a database that provides physical representation combining nodes into one platform. And then third, it’s going to market: since the 3D-IC platform is still new, we have to work with the foundries and OSATs to get some standardization.”

He said that Cadence is engaged with over 20 customers for this new platform.  One of them, imec, the research and innovation hub in nanoelectronics and digital technologies, explained how they are working with the new platform.

Eric Beyne, senior fellow and program director for 3D system integration at imec, said, “With 3D-IC design continuing to gain momentum, there is an increased need to automate the planning and partitioning of a 3D stack die system more efficiently. Through our longstanding collaboration with Cadence, we’ve successfully found automated ways to partition designs to build an optimal 3D stack with increased accessible memory bandwidth that pushes performance and lowers power in advanced-node designs. The integrated memory on the logic flow included in Cadence’s Integrity 3D-IC platform enables cross-die planning, implementation and multi-die STA, which our research teams demonstrated on a multi-core high-performance design.”

Another customer is Lightelligence Inc; its founder and CEO, Yichen Shen, said, “To push AI acceleration using optical computing, we’ve consistently leveraged all the latest, innovative trends in the chip design industry—a key innovation being multi-chiplet stacking. In order to build a heterogeneous multi-chiplet stacked design, it is important to have a fully integrated planning and implementation system, which can represent multiple technology nodes in a single cockpit. The Cadence Integrity 3D-IC platform provides a unified database solution with implementation and early system-level analysis capabilities, including timing signoff and electrothermal analysis. It helps us deliver next-generation innovation using optical computing for AI acceleration.”


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