Cadence: full-flow digital and signoff tools optimized for new 7nm Arm Cortex-A77 CPU -

Cadence: full-flow digital and signoff tools optimized for new 7nm Arm Cortex-A77 CPU


Cadence Design Systems announced that its full-flow digital and signoff tools support the new high-performance, high-efficiency Arm Cortex-A77 CPU for next-generation smartphones, laptops, and other mobile devices. To accelerate the adoption of Arm’s latest processor, Cadence delivered a complete 7nm Rapid Adoption Kit (RAK) that utilizes Arm 7nm POP IP libraries, enabling customers to improve power, performance and area and get to market faster.

The 7nm RAK includes comprehensive documentation and tool scripts that detail how customers can leverage their existing Cadence full-flow digital solution using the latest tool features to achieve PPA goals when creating designs with the Cortex-A77 processor. The complete Cadence RTL-to-GDS flow includes the following digital and signoff tools:

•            Innovus Implementation System: Statistical on-chip variation (SOCV) propagation and IR-driven optimization results in improved timing closure and power integrity for advanced 7nm designs

•            Genus Synthesis Solution: Register-transfer level physical synthesis supports all the latest 7nm advanced-node requirements, resulting in convergent design closure using the Innovus Implementation System

•            Conformal Equivalence Checking: Ensures the accuracy of logic changes and engineering change orders during the implementation flow

•            Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs

•            Tempus Timing Signoff Solution: Offers path-based, signoff-accurate timing analysis, and 7nm physically aware ECO design optimization, providing the quickest path to tapeout

•            Voltus IC Power Integrity Solution: Static and dynamic analysis used during implementation and signoff ensures optimal power distribution design

•            Quantus Extraction Solution: Fulfills all 7nm advanced-node requirements to ensure accurate correlation to final silicon

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