Cadence Design Systems has launched a data platform that pulls in the masses of data being collected by EDA tools, and is using this to enable a suite of AI-driven verification applications that aim to boost coverage and accelerate root cause analysis of design bugs on complex systems on chip (SoCs).
Its new joint enterprise data and AI (JedAI) platform enables engineers to obtain ‘actionable intelligence’ from massive volumes of chip design and verification data, opening the door to a generation of AI-driven design and verification tools that will help improve productivity and power, performance and area (PPA). Cadence said this will result in a generational shift from single-run, single-engine algorithms in EDA to algorithms that leverage big data and artificial intelligence to optimize multiple runs of multiple engines across an entire SoC design and verification flow.
Built on this JedAI platform, the company also announced its Cadence Verisium verification platform, a suite of applications using the big data analytics capability of JedAI to optimize verification workloads, which is natively integrated with the Cadence verification engines. By deploying Verisium, all verification data, including waveforms, coverage, reports and log files, are brought together in JedAI. Machine learning (ML) models are built and other proprietary metrics are mined from this data to enable dramatic improvement in verification productivity. Cadence said that the JedAI platform is able to unify its computational software innovations in data and AI across Verisium verification to Cadence’s Cerebrus Intelligent Chip Explorer’s implementation and Optimality Intelligent System Explorer’s system analysis.
Automating data analytics from EDA tools
Explaining the significance of the new platforms at a launch event in Munich, Germany, Moshik Rubin, a director for marketing at Cadence, hailed the company’s new AI-driven data platform and verification suite as the emergence of EDA 2.0. He said that SoCs are getting increasingly larger and more complex, integrating hundreds of IP. With each of these IP blocks constantly changing as they evolve and improve, it becomes harder to manually correlate the different results and test failures. Determining the root cause of the failure can require dozens of engineers and multiple weeks.
This is where automating the data analytics through an AI-driven platform can help cut verification and debug time, and also reduce the number of engineers needed. The Cadence JedAI platform is meant to make it easier to manage design complexities associated with consumer, hyperscale computing, 5G communications, automotive and mobile applications. Customers using Cadence analog/digital/PCB implementation, verification, and analysis software—and even third-party applications—can use the JedAI platform to unify and analyze all their big data. The platform is cloud-enabled, offering scalable compute resources in a secure design environment from leading cloud providers.
Pat Moorhead, CEO, founder and chief analyst at Moor Insights & Strategy, said, “To enable the semiconductor industry to continue on its strong growth trajectory, it’s critical that the chip design process becomes much more efficient to keep pace with market demands. Improving design processes through AI and big data analytics creates a clear benefit for engineering teams who can now extract key learnings from the vast quantities of EDA data right at their fingertips. The new Cadence JedAI platform is designed to provide users with automated, intelligent design insights and the ability to greatly scale engineering team productivity.”
Venkat Thanvantri, VP of AI R&D at Cadence, added, “Previously, we saw that once a chip design project was completed, the valuable data was deleted to make way for the next project. There are valuable learnings in the legacy data, and the Cadence JedAI platform makes it easy for engineering teams to access these learnings and apply them to future designs to deliver optimal engineering productivity and PPA and ultimately more predictable, higher quality product outcomes.”
According to Rubin, verification is becoming a large part of the design cycle. As SoC complexity continues to rise, verification become a critical path for system time to market, often consuming significantly more compute and human resources than any other silicon engineering task. He told embedded.com that this is the reason Cadence focused on debug as the first application for the JedAI platform. He said, “Debug is the use case where RoI was looking the highest. The main challenge was in finding the right data sets.” He also said that with the shortage of verification engineers, the Verisium platform with AI-driven analytics capability was effectively helping alleviate the issue by providing ‘robot engineers’.
He added. “This will result in a paradigm shift in the way verification engineers will work.”
Cadence released a number of customer endorsements at the launch from MediaTek, Samsung Electronics, STMicroelectronics, and Sony. S. Brian Choi, corporate VP, Samsung Electronics, said, “As SoC complexity continues to grow, SoC-level verification has become a rate-limiting step in our tapeout schedules. We see a great opportunity to leverage AI and big data to dramatically improve design and verification productivity. We are working closely with Cadence to deploy the Verisium platform on our mobile SoC designs and are already seeing impressive results to automatically triage and root cause bugs.”
Meanwhile, Mirella Negro Marcigaglia, STM32 digital verification manager at STMicroelectronics said, “Functional verification has continued to be a major concern to address the rapidly growing complexity of IP and SoC designs in STM32 Microcontrollers. Cadence’s data-driven functional verification platform and apps leveraging AI technology are a very promising approach to contain this problem. We have already observed a significant boost to functional verification productivity, leveraging Verisium AutoTriage, SemanticDiff and WaveMiner. Using the Verisium apps and the Cadence JedAI platform, we aim to quickly achieve a dramatic productivity improvement in triaging and localizing bugs on our IP and SoC designs.”
The initial suite of apps available in the Verisium platform:
- Verisium AutoTriage: Builds ML models that help automate the repetitive task of regression failure triage by predicting and classifying test failures with common root causes.
- Verisium SemanticDiff: Provides an algorithmic solution to compare multiple source code revisions of an IP or SoC, classify these revisions and rank which updates are most disruptive to the system’s behavior to help pinpoint potential bug hotspots.
- Verisium WaveMiner: Applies AI engines to analyze waveforms from multiple runs and determine which signals, at which times, are most likely to represent the root cause of a test failure.
- Verisium PinDown: Integrates with the Cadence JedAI platform and industry-standard revision control systems to build ML models of source code changes, test reports and log files to predict which source code check-ins are most likely to have introduced failures.
- Verisium Debug: Delivers a holistic debug solution from IP to SoC and from single-run to multi-run, with fast interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies. Verisium Debug is natively integrated with the Cadence JedAI Platform and other Verisium apps to enable AI-driven root cause analysis with the support of simultaneous automatic comparison of passing and failing tests.
- Verisium Manager: Brings Cadence’s full flow IP and SoC-level verification management solution with verification planning, job scheduling, and multi-engine coverage natively onto the Cadence JedAI platform and extends it to support AI-driven testsuite optimization to improve compute farm efficiency. Verisium Manager also integrates directly with other Verisium apps, enabling interactive push-button deployment of the complete Verisium platform from a unified browser-based management console.
The Verisium verification platform is part of the Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper formal Verification Platform and the Helium™ Virtual and Hybrid Studio. please visit.
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